公开(公告)号：US20170054021A1

公开(公告)日：2017-02-23

申请号：US15208783

申请日：2016-07-13

Applicant: IMEC VZW

Inventor： Bernardette Kunert ,  Robert Langer

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/04 ,  H01L29/205

CPC classification number: H01L29/7846 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/785

Abstract: The present disclosure relates to a semiconductor structure and a method of preparation including a silicon monocrystalline substrate, and a III-V structure abutting the silicon monocrystalline substrate. The semiconductor structure includes an InaGabAs structure overlaying the III-V structure, where a is from 0.40 to 1, b from 0 to 0.60, and a+b equal to 1.00. The III-V structure has a top surface facing away from the silicon substrate. The top surface is GagXxPpSbsZz, where X includes one or more group III elements other than Ga and Z is one or more group V elements other than P or Sb. g is from 0.80 to 1.00, x is from 0 to 0.20, z is from 0 to 0.30, p is from 0.10 to 0.55, and s is from 0.50 to 0.80, g+x is equal to 1.00 and p+s+z is equal to 1.00.

Abstract translation: 本公开涉及一种半导体结构和包括硅单晶衬底的制备方法以及邻接硅单晶衬底的III-V结构。 半导体结构包括覆盖III-V结构的InaGabAs结构，其中a为0.40至1，b为0至0.60，a + b等于1.00。 III-V结构具有背离硅衬底的顶表面。 上表面是GagXxPpSbsZz，其中X包括除Ga之外的一个或多个III族元素，Z是除P或Sb以外的一种或多种V族元素。 g为0.80〜1.00，x为0〜0.20，z为0〜0.30，p为0.10〜0.55，s为0.50〜0.80，g + x为1.00，p + s + z为 等于1.00。