公开(公告)号：US20180165144A1

公开(公告)日：2018-06-14

申请号：US15372734

申请日：2016-12-08

Applicant: INTEL CORPORATION

Inventor： Ashok RAJ ,  Narayan RANGANATHAN ,  Mohan J. KUMAR ,  Vincent J. ZIMMER

IPC: G06F11/07 ,  G06F9/30

CPC classification number: G06F11/0787 ,  G06F9/3016 ,  G06F11/0766

Abstract: A processor includes an instruction decoder to receive an instruction to perform a machine check operation, the instruction having a first operand and a second operand. The processor further includes a machine check logic coupled to the instruction decoder to determine that the instruction is to determine a type of a machine check bank based on a command value stored in a first storage location indicated by the first operand, to determine a type of a machine check bank identified by a machine check bank identifier (ID) stored in a second storage location indicated by the second operand, and to store the determined type of the machine check bank in the first storage location indicated by the first operand.

公开(公告)号：US20160321127A1

公开(公告)日：2016-11-03

申请号：US15206853

申请日：2016-07-11

Applicant: INTEL CORPORATION

Inventor： Ashok RAJ ,  Narayan RANGANATHAN

IPC: G06F11/07 ,  G06F11/14

CPC classification number: G06F11/079 ,  G06F11/0706 ,  G06F11/0751 ,  G06F11/0787 ,  G06F11/1417 ,  G06F2201/805

Abstract: A computing system can include a machine check counter (MCC) including a current value. The current value indicates a system reboot resetting hardware of the computing system. The machine check counter includes a model specific register including a counter indicating the current value, the current value to be incremented upon the system reboot.