公开(公告)号：US20230395506A1

公开(公告)日：2023-12-07

申请号：US17833708

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Miriam Reshotko ,  Elijah Karpov ,  Mark Anders ,  Gauri Auluck ,  Shakuntala Sundararajan ,  Michael Makowski ,  Caleb Barrett

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L23/5226 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53266

Abstract: Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.