公开(公告)号：US20240332064A1

公开(公告)日：2024-10-03

申请号：US18126702

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Shaun MILLS ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L21/76808 ,  H01L21/76804 ,  H01L21/823475 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53257

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a package that has a transistor layer with a front side metal interconnect layer and a back side metal contact and interconnect layer. In particular, back side metal contact and interconnect layers may be patterned before a transistor layer, or other device layer, is formed on the patterned layers and before front side metal interconnect layers are formed on the transistor layer. Other embodiments may be described and/or claimed.