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公开(公告)号：US20220406704A1
公开(公告)日：2022-12-22
申请号：US17304466
申请日：2021-06-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Yann Mignot , CHANRO PARK , Hsueh-Chung Chen
IPC: H01L23/528 , H01L23/532 , H01L21/768
Abstract: A top cap layer covering a first metal line and a second metal line, horizontally between the first metal line and the second metal line is, in sequential order, a post cap liner, an air gap and the post cap liner. A first set of metal lines embedded in an upper surface of a dielectric, a second set of metal lines embedded below the dielectric and above the electronic components, a post cap liner covering the first set of metal lines, a cavity which dissects a first metal line of the first set of metal lines and extends to a second metal line of the second set of metal lines and dissects the second set of metal lines. Forming a cavity in a first metal line embedded in an upper surface of a dielectric, where the first metal line and the dielectric are covered by a top cap layer.
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公开(公告)号：US11195995B2
公开(公告)日：2021-12-07
申请号：US16735020
申请日：2020-01-06
Applicant: International Business Machines Corporation
Inventor： Chi-Chun Liu , Yann Mignot , Ekmini Anuja De Silva , Nelson Felix , John Christopher Arnold
Abstract: A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.
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公开(公告)号：US20210328041A1
公开(公告)日：2021-10-21
申请号：US16849072
申请日：2020-04-15
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Yann Mignot , Indira Seshadri , Su Chen Fan , Christopher J. Waskiewicz , Eric Miller
IPC: H01L29/66 , H01L29/49 , H01L29/417 , H01L29/78 , H01L21/28
Abstract: A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.
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公开(公告)号：US20210287940A1
公开(公告)日：2021-09-16
申请号：US16817988
申请日：2020-03-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Yann Mignot , Chanro Park , Chih-Chao Yang , Injo Ok , Hsueh-Chung Chen
IPC: H01L21/768
Abstract: Embodiments of the present invention disclose a method forming a via and a trench. By utilizing a first etching process, a first metal layer of a multi-layered device to form a via, wherein the multi-layered device comprises the first metal layer and a second metal layer, wherein the first metal layer is formed directly on top of the second metal layer, wherein the second metal layer acts as an etch stop for the first etching process, wherein the first etching process does not affect the second metal layer. By utilizing a second etching process, the second metal layer of the multi-layered device to form a trench, wherein first metal layer is not affected by the second etching process, wherein the first etching process and the second etching process are two different etching process.
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公开(公告)号：US20210159117A1
公开(公告)日：2021-05-27
申请号：US16693610
申请日：2019-11-25
Applicant: International Business Machines Corporation
Inventor： Junli Wang , Hsueh-Chung Chen , Su Chen Fan , Yann Mignot , Lawrence A. Clevenger
IPC: H01L21/768 , H01L23/532 , H01L21/8234 , H01L21/311 , H01L23/528 , H01L23/522
Abstract: A semiconductor device includes a first interconnect structure formed in an Mx level of the semiconductor device, the Mx level includes a third interlevel dielectric layer located above a second capping layer, a first trench within the third interlevel dielectric layer extending through the second capping layer to expose a top surface of a contact structure located below the second capping layer, the contact structure is located within a second interlevel dielectric layer, a second metal liner conformally deposited within the first trench, and a first seed layer conformally deposited above the second metal liner, the first seed layer includes a metal manganese film. A first thermal annealing process is conducted on the semiconductor device to form a first barrier liner underneath the second metal liner to prevent diffusion of conductive metals.
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公开(公告)号：US10937653B2
公开(公告)日：2021-03-02
申请号：US16669835
申请日：2019-10-31
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Hsueh-Chung Chen , Yongan Xu , Lawrence A. Clevenger , Yann Mignot , Cornelius Brown Peethala
IPC: H01L21/033 , H01L21/027 , H01L21/02 , H01L21/3105 , G03F7/00 , G03F7/16 , G03F7/20 , G03F7/09
Abstract: A method for fabricating a semiconductor device integrating a multiple patterning scheme includes forming a memorization layer over a plurality of mandrels and a plurality of non-mandrels, and applying an exposure scheme to the memorization layer to form at least one mandrel cut pattern and at least one non-mandrel cut pattern.
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公开(公告)号：US10825720B2
公开(公告)日：2020-11-03
申请号：US16112286
申请日：2018-08-24
Applicant: International Business Machines Corporation
Inventor： Yann Mignot , Yongan Xu , Muthumanickam Sankarapandian
IPC: H01L23/48 , H01L21/768 , H01L23/532 , H01L21/033 , H01L21/02 , H01L21/311
Abstract: Techniques for single trench damascene interconnect formation using TiN HMO are provided. In one aspect, a method for forming interconnects on a substrate includes: forming an underlayer on the substrate; forming a hardmask on the underlayer; patterning trenches in the hardmask that extend down to the underlayer; forming the interconnects in the trenches; removing the hardmask; and burying the interconnects in an ILD. The trenches can be patterned in the hardmask using a process such as sidewall image transfer. An interconnect structure is also provided.
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公开(公告)号：US10741452B2
公开(公告)日：2020-08-11
申请号：US16173378
申请日：2018-10-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Eric R. Miller , Stuart A. Sieg , Yann Mignot , Indira Seshadri , Christopher J. Waskiewicz
IPC: H01L21/8234 , H01L21/308 , H01L21/033 , H01L29/66 , H01L27/088
Abstract: Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.
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公开(公告)号：US10692776B2
公开(公告)日：2020-06-23
申请号：US16181977
申请日：2018-11-06
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Eric R. Miller , Marc Bergendahl , Kangguo Cheng , Yann Mignot
IPC: H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/66
Abstract: A semiconductor device includes etching fins into a bulk substrate in an active region, the bulk substrate including an intermediate layer formed over a base layer and a first semiconductor layer formed over the intermediate layer such that the fins extend through the first semiconductor layer into the intermediate layer to form tapered bottom portions of the fins within the intermediate layer and vertical fin sidewalls of a semiconductor portions of the fins within the first semiconductor layer. A second semiconductor layer is formed around the tapered bottom portions below the semiconductor portions of the fins such that the second semiconductor layer covers the tapered bottom portions to form a top surface proximal to the semiconductor portions of the fins that is substantially parallel to a bottom surface of the top surface of the base layer. A gate structure is formed around the fins.
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公开(公告)号：US20200144131A1
公开(公告)日：2020-05-07
申请号：US16181977
申请日：2018-11-06
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Eric R. Miller , Marc Bergendahl , Kangguo Cheng , Yann Mignot
IPC: H01L21/8238 , H01L27/092
Abstract: A semiconductor device includes etching fins into a bulk substrate in an active region, the bulk substrate including an intermediate layer formed over a base layer and a first semiconductor layer formed over the intermediate layer such that the fins extend through the first semiconductor layer into the intermediate layer to form tapered bottom portions of the fins within the intermediate layer and vertical fin sidewalls of a semiconductor portions of the fins within the first semiconductor layer. A second semiconductor layer is formed around the tapered bottom portions below the semiconductor portions of the fins such that the second semiconductor layer covers the tapered bottom portions to form a top surface proximal to the semiconductor portions of the fins that is substantially parallel to a bottom surface of the top surface of the base layer. A gate structure is formed around the fins.
