公开(公告)号：US08058658B2

公开(公告)日：2011-11-15

申请号：US12421130

申请日：2009-04-09

申请人： Sang-Heung Lee ,  Hae Cheon Kim ,  Dong Min Kang ,  Dong-Young Kim ,  Jae Kyoung Mun ,  Hokyun Ahn ,  Jong-Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Eun Soo Nam

发明人： Sang-Heung Lee ,  Hae Cheon Kim ,  Dong Min Kang ,  Dong-Young Kim ,  Jae Kyoung Mun ,  Hokyun Ahn ,  Jong-Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Eun Soo Nam

IPC分类号： H01L27/15

CPC分类号： H01L25/167 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/48137 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/30107 ,  H01L2924/00

摘要： Provided is a high-speed optical interconnection device. The high-speed optical interconnection device includes a first semiconductor chip, light emitters, optical detectors, and a second semiconductor chip, which are disposed on a silicon-on-insulator (SOI) substrate. The light emitters receive electrical signals from the first semiconductor chip to output optical signals. The optical detectors detect the optical signals to convert the optical signals into electrical signals. The second semiconductor chip receives the electrical signals converted by the optical detectors.

摘要翻译： 提供了一种高速光互连装置。 高速光互连装置包括设置在绝缘体上硅（SOI））衬底上的第一半导体芯片，发光体，光检测器和第二半导体芯片。 光发射器接收来自第一半导体芯片的电信号以输出光信号。 光检测器检测光信号，将光信号转换为电信号。 第二半导体芯片接收由光学检测器转换的电信号。

公开(公告)号：US07902572B2

公开(公告)日：2011-03-08

申请号：US12122805

申请日：2008-05-19

申请人： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

发明人： Ho Kyun Ahn ,  Jong Won Lim ,  Jae Kyoung Mun ,  Hong Gu Ji ,  Woo Jin Chang ,  Hea Cheon Kim

IPC分类号： H01L31/072

CPC分类号： H01L29/812 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/778

摘要： A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

摘要翻译： 提供了具有头部比脚部宽的T形或/或G字形精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。 使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。 由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。 此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

公开(公告)号：US07419862B2

公开(公告)日：2008-09-02

申请号：US11446750

申请日：2006-06-05

申请人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hea Cheon Kim

发明人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hea Cheon Kim

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7784 ,  H01L29/1029 ,  H01L29/66462

摘要： Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT). The method includes the steps of: preparing a substrate including a channel layer and a capping layer that is the uppermost layer; forming a source and a drain on the capping layer; forming a first protective layer on the entire surface of the resultant structure and then patterning the first protective layer to expose a portion of the capping layer in a channel region; removing the exposed portion of the capping layer to form a first recess structure; forming a second protective layer on the entire surface of the resultant structure and then patterning the second protective layer to expose a portion of the substrate in the first recess structure so that a second recess structure is formed; forming a multilayered photoresist layer on the entire surface of the resultant structure and then patterning the multilayered photoresist layer to expose a portion of the substrate through the second recess structure and form a gate-shaped opening; and depositing a metal layer to fill the gate-shaped opening and then removing the multilayered photoresist layer to form a gate connected to the substrate through the second recess structure.

摘要翻译： 提供了制造假象高电子迁移率晶体管（PHEMT）的方法。 该方法包括以下步骤：制备包括沟道层和作为最上层的覆盖层的衬底; 在封盖层上形成源极和漏极; 在所得结构的整个表面上形成第一保护层，然后图案化第一保护层以暴露沟道区中的覆盖层的一部分; 去除所述覆盖层的暴露部分以形成第一凹陷结构; 在所得结构的整个表面上形成第二保护层，然后构图第二保护层，以暴露第一凹陷结构中的基底的一部分，从而形成第二凹陷结构; 在所得结构的整个表面上形成多层光致抗蚀剂层，然后构图多层光致抗蚀剂层，以通过第二凹陷结构暴露出基板的一部分并形成栅极形开口; 以及沉积金属层以填充所述栅极开口，然后移除所述多层光致抗蚀剂层，以形成通过所述第二凹陷结构连接到所述衬底的栅极。

公开(公告)号：US20070134862A1

公开(公告)日：2007-06-14

申请号：US11446750

申请日：2006-06-05

申请人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hea Cheon Kim

发明人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hea Cheon Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/7784 ,  H01L29/1029 ,  H01L29/66462

摘要： Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT). The method includes the steps of: preparing a substrate including a channel layer and a capping layer that is the uppermost layer; forming a source and a drain on the capping layer; forming a first protective layer on the entire surface of the resultant structure and then patterning the first protective layer to expose a portion of the capping layer in a channel region; removing the exposed portion of the capping layer to form a first recess structure; forming a second protective layer on the entire surface of the resultant structure and then patterning the second protective layer to expose a portion of the substrate in the first recess structure so that a second recess structure is formed; forming a multilayered photoresist layer on the entire surface of the resultant structure and then patterning the multilayered photoresist layer to expose a portion of the substrate through the second recess structure and form a gate-shaped opening; and depositing a metal layer to fill the gate-shaped opening and then removing the multilayered photoresist layer to form a gate connected to the substrate through the second recess structure.

摘要翻译： 提供了制造假象高电子迁移率晶体管（PHEMT）的方法。 该方法包括以下步骤：制备包括沟道层和作为最上层的覆盖层的衬底; 在封盖层上形成源极和漏极; 在所得结构的整个表面上形成第一保护层，然后图案化第一保护层以暴露沟道区中的覆盖层的一部分; 去除所述覆盖层的暴露部分以形成第一凹陷结构; 在所得结构的整个表面上形成第二保护层，然后构图第二保护层，以暴露第一凹陷结构中的基底的一部分，从而形成第二凹陷结构; 在所得结构的整个表面上形成多层光致抗蚀剂层，然后构图多层光致抗蚀剂层，以通过第二凹陷结构暴露出基板的一部分并形成栅极形开口; 以及沉积金属层以填充所述栅极开口，然后移除所述多层光致抗蚀剂层，以形成通过所述第二凹陷结构连接到所述衬底的栅极。

公开(公告)号：US07429894B2

公开(公告)日：2008-09-30

申请号：US11519668

申请日：2006-09-12

申请人： Woo Jin Chang ,  Jae Kyoung Mun ,  Haecheon Kim ,  Jong Won Lim ,  Hong Gu Ji ,  Ho Kyun Ahn

发明人： Woo Jin Chang ,  Jae Kyoung Mun ,  Haecheon Kim ,  Jong Won Lim ,  Hong Gu Ji ,  Ho Kyun Ahn

IPC分类号： H03F3/68

CPC分类号： H03F3/602 ,  H03F3/211 ,  H03F2200/366 ,  H03F2200/447 ,  H03F2200/543 ,  H03F2203/21178

摘要： Provided is a power device having a connection structure compensating for a reactance component, in which transistors are arranged and connected to minimize deterioration of transistor properties caused by heat by compensating for a reactance component causing a phase difference due to transmission lines used for connecting a plurality of transistors in parallel such that the power device to be used for a high-frequency power amplifier outputs high power, and transmitting heat generated by high output power to a heat sink to be dissipated.

摘要翻译： 提供了具有补偿电抗分量的连接结构的功率器件，其中配置并连接晶体管，以通过补偿导致由于用于连接多个元件的传输线引起的相位差的电抗分量来最小化由热引起的晶体管性质的劣化 的晶体管并联，使得用于高频功率放大器的功率器件输出高功率，并将由高输出功率产生的热量传输到散热器。

公开(公告)号：US20110143507A1

公开(公告)日：2011-06-16

申请号：US13004750

申请日：2011-01-11

申请人： Jae Kyoung Mun ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

发明人： Jae Kyoung Mun ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/7785 ,  H01L29/42316

摘要： Provided are a transistor of a semiconductor device and a method of fabricating the same. The transistor of a semiconductor device includes an epitaxial substrate having a buffer layer, a first silicon (Si) planar doped layer, a first conductive layer, a second Si planar doped layer having a different dopant concentration from the first Si planar doped layer, and a second conductive layer, which are sequentially formed on a semi-insulating substrate; a source electrode and a drain electrode formed on both sides of the second conductive layer to penetrate the first Si planar doped layer to a predetermined depth to form an ohmic contact; and a gate electrode formed on the second conductive layer between the source electrode and the drain electrode to form a contact with the second conductive layer, wherein the gate electrode, the source electrode and the drain electrode are electrically insulated by an insulating layer, and a predetermined part of an upper part of the gate electrode is formed to overlap at least one of the source electrode and the drain electrode. Therefore, a maximum voltage that can be applied to the switching device is increased due to increases of a gate turn-on voltage and a breakdown voltage, and decrease of a parallel conduction component. As a result of this improved power handling capability, high-power and low-distortion characteristics and high isolation can be expected from the switching device.

摘要翻译： 提供半导体器件的晶体管及其制造方法。 半导体器件的晶体管包括具有缓冲层，第一硅（Si）平面掺杂层，第一导电层，具有与第一Si平面掺杂层不同的掺杂剂浓度的第二Si平面掺杂层的外延衬底，以及 第二导电层，其依次形成在半绝缘基板上; 源电极和漏电极，形成在第二导电层的两侧，以将第一Si平面掺杂层穿透到预定深度以形成欧姆接触; 以及形成在所述源电极和所述漏电极之间的所述第二导电层上的栅电极，以与所述第二导电层形成接触，其中所述栅电极，所述源电极和所述漏极由绝缘层电绝缘， 栅电极的上部的预定部分形成为与源电极和漏电极中的至少一个重叠。 因此，由于栅极导通电压和击穿电压的增加以及并联导通分量的降低，可以施加到开关器件的最大电压增加。 由于这种改进的功率处理能力，可以期望从开关器件获得高功率和低失真特性以及高隔离度。

公开(公告)号：US08697507B2

公开(公告)日：2014-04-15

申请号：US13004750

申请日：2011-01-11

申请人： Jae Kyoung Mun ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

发明人： Jae Kyoung Mun ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

IPC分类号： H01L21/338

CPC分类号： H01L29/7785 ,  H01L29/42316

摘要： Provided are a transistor of a semiconductor device and a method of fabricating the same. The transistor of a semiconductor device includes an epitaxial substrate having a buffer layer, a first silicon (Si) planar doped layer, a first conductive layer, a second Si planar doped layer having a different dopant concentration from the first Si planar doped layer, and a second conductive layer, which are sequentially formed on a semi-insulating substrate; a source electrode and a drain electrode formed on both sides of the second conductive layer to penetrate the first Si planar doped layer to a predetermined depth to form an ohmic contact; and a gate electrode formed on the second conductive layer between the source electrode and the drain electrode to form a contact with the second conductive layer, wherein the gate electrode, the source electrode and the drain electrode are electrically insulated by an insulating layer, and a predetermined part of an upper part of the gate electrode is formed to overlap at least one of the source electrode and the drain electrode. Therefore, a maximum voltage that can be applied to the switching device is increased due to increases of a gate turn-on voltage and a breakdown voltage, and decrease of a parallel conduction component. As a result of this improved power handling capability, high-power and low-distortion characteristics and high isolation can be expected from the switching device.

摘要翻译： 提供半导体器件的晶体管及其制造方法。 半导体器件的晶体管包括具有缓冲层，第一硅（Si）平面掺杂层，第一导电层，具有与第一Si平面掺杂层不同的掺杂剂浓度的第二Si平面掺杂层的外延衬底，以及 第二导电层，其依次形成在半绝缘基板上; 源电极和漏电极，形成在第二导电层的两侧，以将第一Si平面掺杂层穿透到预定深度以形成欧姆接触; 以及形成在所述源电极和所述漏电极之间的所述第二导电层上的栅电极，以与所述第二导电层形成接触，其中所述栅电极，所述源电极和所述漏极由绝缘层电绝缘， 栅电极的上部的预定部分形成为与源电极和漏电极中的至少一个重叠。 因此，由于栅极导通电压和击穿电压的增加以及并联导通分量的降低，可以施加到开关器件的最大电压增加。 由于这种改进的功率处理能力，可以期望从开关器件获得高功率和低失真特性以及高隔离度。

公开(公告)号：US08772833B2

公开(公告)日：2014-07-08

申请号：US13592560

申请日：2012-08-23

申请人： Woo Jin Chang ,  Jong Won Lim ,  Ho Kyun Ahn ,  Sang Choon Ko ,  Sung Bum Bae ,  Chull Won Ju ,  Young Rak Park ,  Jae Kyoung Mun ,  Eun Soo Nam

发明人： Woo Jin Chang ,  Jong Won Lim ,  Ho Kyun Ahn ,  Sang Choon Ko ,  Sung Bum Bae ,  Chull Won Ju ,  Young Rak Park ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC分类号： H01L29/15

CPC分类号： H01L29/66901 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

摘要： Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.

摘要翻译： 公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。 根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。

公开(公告)号：US20130069127A1

公开(公告)日：2013-03-21

申请号：US13556377

申请日：2012-07-24

申请人： Ho Kyun AHN ,  Jong-Won Lim ,  Sung Bum Bae ,  Sang Choon Ko ,  Young Rak Park ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Eun Soo Nam ,  Jeong Jin Kim ,  Chull Won Ju

发明人： Ho Kyun AHN ,  Jong-Won Lim ,  Sung Bum Bae ,  Sang Choon Ko ,  Young Rak Park ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Eun Soo Nam ,  Jeong Jin Kim ,  Chull Won Ju

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/8128

摘要： A method for fabricating a field effect transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a cap layer, an ohmic metal layer and an insulating layer on a substrate; forming multilayered photoresists on the insulating layer; patterning the multilayered photoresists to form a photoresist pattern including a first opening for gate electrode and a second opening for field electrode; etching the insulating layer by using the photoresist pattern as an etching mask so that the insulating layer in the first opening is etched more deeply and the cap layer is exposed through the first opening; etching the cap layer exposed by etching the insulating layer through the first opening to form a gate recess region; and depositing a metal on the gate recess region and the etched insulating layer to form a gate-field electrode layer.

摘要翻译： 根据本公开的示例性实施例的制造场效应晶体管的方法包括：在衬底上形成有源层，覆盖层，欧姆金属层和绝缘层; 在所述绝缘层上形成多层光致抗蚀剂; 图案化多层光致抗蚀剂以形成包括用于栅电极的第一开口和场电极的第二开口的光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻绝缘层，使得第一开口中的绝缘层被更深地蚀刻并且盖层通过第一开口暴露; 通过蚀刻绝缘层通过第一开口蚀刻暴露的盖层，以形成栅极凹陷区域; 以及在所述栅极凹部区域和所述蚀刻绝缘层上沉积金属以形成栅极电极层。

公开(公告)号：US07893462B2

公开(公告)日：2011-02-22

申请号：US11280608

申请日：2005-11-15

申请人： Jae Kyoung Mun ,  Hung Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

发明人： Jae Kyoung Mun ,  Hung Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

IPC分类号： H01L29/66

CPC分类号： H01L29/7785 ,  H01L29/42316

摘要： Provided are a transistor of a semiconductor device and a method of fabricating the same. The transistor of a semiconductor device includes an epitaxial substrate having a buffer layer, a first silicon (Si) planar doped layer, a first conductive layer, a second Si planar doped layer having a different dopant concentration from the first Si planar doped layer, and a second conductive layer, which are sequentially formed on a semi-insulating substrate; a source electrode and a drain electrode formed on both sides of the second conductive layer to penetrate the first Si planar doped layer to a predetermined depth to form an ohmic contact; and a gate electrode formed on the second conductive layer between the source electrode and the drain electrode to form a contact with the second conductive layer, wherein the gate electrode, the source electrode and the drain electrode are electrically insulated by an insulating layer, and a predetermined part of an upper part of the gate electrode is formed to overlap at least one of the source electrode and the drain electrode. Therefore, a maximum voltage that can be applied to the switching device is increased due to increases of a gate turn-on voltage and a breakdown voltage, and decrease of a parallel conduction component. As a result of this improved power handling capability, high-power and low-distortion characteristics and high isolation can be expected from the switching device.

摘要翻译： 提供半导体器件的晶体管及其制造方法。 半导体器件的晶体管包括具有缓冲层，第一硅（Si）平面掺杂层，第一导电层，具有与第一Si平面掺杂层不同的掺杂剂浓度的第二Si平面掺杂层的外延衬底，以及 第二导电层，其依次形成在半绝缘基板上; 源电极和漏电极，形成在第二导电层的两侧，以将第一Si平面掺杂层穿透到预定深度以形成欧姆接触; 以及形成在所述源电极和所述漏电极之间的所述第二导电层上的栅电极，以与所述第二导电层形成接触，其中所述栅电极，所述源电极和所述漏极由绝缘层电绝缘， 栅电极的上部的预定部分形成为与源电极和漏电极中的至少一个重叠。 因此，由于栅极导通电压和击穿电压的增加以及并联导通分量的降低，可以施加到开关器件的最大电压增加。 由于这种改进的功率处理能力，可以期望从开关器件获得高功率和低失真特性以及高隔离度。