公开(公告)号：US20110107289A1

公开(公告)日：2011-05-05

申请号：US12609370

申请日：2009-10-30

Applicant: Aravind Oommen ,  Hemanga Das ,  Krishnan Sundaresan

Inventor： Aravind Oommen ,  Hemanga Das ,  Krishnan Sundaresan

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/78

Abstract: A method and system of merging gated-clock domains in a semiconductor design includes producing, for each subset of clock gating functions in an initial set of clock gating functions, a set of quantified functions produced by existentially quantifying each clock gating function in the subset over a set of variables that are not part of the support sets of the other clock gating functions of the subset. If the set of quantified functions are equal, selecting one as a super clock gating function and adding it to the set of super clock gating functions. The set of super clock gating functions are sorted according to a criterion and the best is selected and added to the set of final clock gating functions. The remaining super clock gating functions are modified to prevent flip-flops gated by the selected super clock gating function from being gated by remaining super clock gating functions.

Abstract translation: 在半导体设计中合并门控时钟域的方法和系统包括：对初始的时钟选通功能集合中的时钟门控功能的每个子集产生一组定量的函数，其通过存在量化子集中的每个时钟门控函数产生 一组不是子集的其他时钟门控功能的支持集的一部分的变量。 如果一组量化函数相等，则选择一个作为超时钟门控功能，并将其添加到一组超时钟门控功能。 该超级时钟门控功能集合根据标准进行排序，并选择最佳选项并将其添加到最终时钟门控功能组中。 剩余的超级时钟门控功能被修改，以防止由所选择的超级时钟门控功能选通的触发器被剩余的超时钟门控功能选通。