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    Sub-word line drivers for integrated circuit memory devices and related methods
    11.
    发明授权
    Sub-word line drivers for integrated circuit memory devices and related methods 失效
    用于集成电路存储器件的子字线驱动器及相关方法

    公开(公告)号：US5761135A

    公开(公告)日：1998-06-02

    申请号：US706223

    申请日：1996-09-03

    申请人： Kyu-chan Lee

    发明人： Kyu-chan Lee

    IPC分类号： G11C11/401 ,  G11C8/08 ,  G11C8/14 ,  G11C11/407 ,  G11C7/00

    CPC分类号： G11C8/08 ,  G11C8/14

    摘要： An integrated circuit memory device includes an array of memory cells arranged into rows and columns. A main word line decoder receives a first portion of a row address and generates a main word line activation signal on a predetermined word line in response thereto. A word driver predecoder receives a second portion of the row address and generates a sub-row activation signal in response thereto. A sub-word line driver generates a sub-word line activation signal on an output node. This sub-word line driver includes a pull-down transistor, a pull-up transistor, and a driving transistor. The pull-down transistor electrically connects the output node to a ground terminal in response to an inverse of the sub-row activation signal. The pull-up transistor transfers the sub-row activation signal to the output node in response to the main word line activation signal. The driving transistor transfers the main word line activation signal to the output node in response to the sub-row activation signal. A sub-word line electrically connects the output node and a predetermined memory cell so that the predetermined memory cell is activated in response to the sub-word line activation signal.

    摘要翻译： 集成电路存储器件包括排列成行和列的存储单元阵列。 主字线解码器接收行地址的第一部分，并响应于此在一预定字线上产生主字线激活信号。 字驱动器预解码器接收行地址的第二部分并响应于此生成子行激活信号。 子字线驱动器在输出节点上产生子字线激活信号。 该子字线驱动器包括下拉晶体管，上拉晶体管和驱动晶体管。 下拉晶体管响应于子行激活信号的倒数将输出节点电连接到接地端子。 上拉晶体管响应于主字线激活信号将子行激活信号传送到输出节点。 驱动晶体管响应于子行激活信号将主字线激活信号传送到输出节点。 子字线路电连接输出节点和预定的存储器单元，使得响应于子字线激活信号激活预定存储器单元。

    DISPLAY APPARATUS AND TIMING CONTROLLER FOR CALIBRATING GRAYSCALE DATA AND METHOD FOR DRIVING PANEL THEREOF
    13.
    发明申请
    DISPLAY APPARATUS AND TIMING CONTROLLER FOR CALIBRATING GRAYSCALE DATA AND METHOD FOR DRIVING PANEL THEREOF 有权
    用于校准灰度数据的显示装置和时序控制器及其驱动面板的方法

    公开(公告)号：US20100085387A1

    公开(公告)日：2010-04-08

    申请号：US12476716

    申请日：2009-06-02

    申请人： Sung-soo Kim ,  Kyu-chan Lee ,  Hyeong-sik Choi

    发明人： Sung-soo Kim ,  Kyu-chan Lee ,  Hyeong-sik Choi

    IPC分类号： G09G5/10

    CPC分类号： G09G3/3648 ,  G09G2310/06 ,  G09G2320/0252 ,  G09G2320/0257 ,  G09G2340/16 ,  G09G2360/18

    摘要： A display apparatus for calibrating a grayscale data including a timing controller, and a method for driving a panel are provided. A display apparatus includes a timing controller which calibrates the grayscale data of the current frame using the grayscale data of the previous and the current frame and a driving unit which drives a panel using the calibrated grayscale data of the current frame. By generating calibrated grayscale data which are variable according to the change of grayscale, response times of liquid crystal may be improved.

    摘要翻译： 提供了用于校准包括定时控制器的灰度数据的显示装置和用于驱动面板的方法。 显示装置包括使用前一帧和当前帧的灰阶数据来校准当前帧的灰阶数据的定时控制器，以及使用当前帧的校准灰度数据来驱动面板的驱动单元。 通过生成根据灰度变化可变的校准灰度数据，可以提高液晶的响应时间。

    Integrated circuit memories including fuses between a decoder and a memory array for disabling defective storage cells in the memory array
    14.
    发明授权
    Integrated circuit memories including fuses between a decoder and a memory array for disabling defective storage cells in the memory array 失效
    集成电路存储器，包括解码器和用于禁止存储器阵列中的有缺陷的存储单元的存储器阵列之间的熔丝

    公开(公告)号：US06215715B1

    公开(公告)日：2001-04-10

    申请号：US09346567

    申请日：1999-07-01

    申请人： Kyu-chan Lee ,  Chul-woo Yi

    发明人： Kyu-chan Lee ,  Chul-woo Yi

    IPC分类号： G11C800

    CPC分类号： G11C29/785

    摘要： An integrated circuit memory device includes a two-dimensional memory array in which the first and second dimensions extend in first and second directions respectively. The memory device further includes a decoder for the first dimension and a plurality of fuses between the decoder and the memory array. Upon encountering a defective storage cell in the memory array, the appropriate fuse can be cut to physically segregate the decoder from the defective cell. This allows the memory to operate without any delay inserted for switching to a spare or redundant memory array of storage cells, thus maximizing the memory operating speed. In a preferred embodiment, the fuses are arranged such that the relative spacing between the fuses proceeds substantially along the second direction and the fuses are oriented lengthwise in the first direction. By following this arrangement, the impact on the layout area for the memory device is minimal.

    摘要翻译： 集成电路存储器件包括二维存储器阵列，其中第一和第二尺寸分别在第一和第二方向上延伸。 存储器件还包括用于第一维度的解码器和解码器与存储器阵列之间的多个熔丝。 当遇到存储器阵列中的有缺陷的存储单元时，可以切割适当的熔丝以使解码器与有缺陷的单元物理隔离。 这允许存储器在没有任何延迟的情况下操作以切换到存储单元的备用或冗余存储器阵列，从而最大化存储器操作速度。 在优选实施例中，保险丝被布置成使得熔丝之间的相对间隔基本上沿着第二方向进行，并且熔丝在第一方向上纵向定向。 通过遵循这种布置，对存储器件的布局区域的影响是最小的。

    Semiconductor memory device having hierarchical input/output line structure and method for arranging the same
    15.
    发明授权
    Semiconductor memory device having hierarchical input/output line structure and method for arranging the same 失效
    具有分级输入/输出线结构的半导体存储器件及其布置方法

    公开(公告)号：US5949697A

    公开(公告)日：1999-09-07

    申请号：US988289

    申请日：1997-12-10

    申请人： Kyu-chan Lee

    发明人： Kyu-chan Lee

    IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/10 ,  G11C8/14 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C5/02

    CPC分类号： G11C7/1006 ,  G11C8/14

    摘要： A semiconductor memory device having a hierarchical input/output line structure and a method for arranging the same are provided. The semiconductor memory device includes a sub-array including a plurality of memory cells. The semiconductor memory device further includes a sense amplifier for sensing and amplifying the data of the memory cells of the sub-array. The semiconductor memory device further includes a sub-word line driver for driving the word lines of the memory cells. The semiconductor memory device further includes a local input/output line for receiving and transmitting the output signal of the sense amplifier. The semiconductor memory device further includes a global input/output line for receiving and transmitting the signal of the local input/output line. The semiconductor memory device further includes switching means for transmitting the signal of the local input/output line to the global input/output line in response to predetermined control signals. A conjunction area is formed in an intersecting area between the sense amplifier and the sub-word line driver. In particular, the switching means are separated and arranged in the conjunction areas in which the local input/output line intersects the global input/output line. A P driver and an N driver for driving the sense amplifier are arranged in the same conjunction.

    摘要翻译： 提供了具有分级输入/输出线结构的半导体存储器件及其布置方法。 半导体存储器件包括包括多个存储单元的子阵列。 半导体存储器件还包括用于感测和放大子阵列的存储单元的数据的读出放大器。 半导体存储器件还包括用于驱动存储器单元的字线的子字线驱动器。 半导体存储器件还包括用于接收和发送读出放大器的输出信号的本地输入/输出线。 半导体存储器件还包括用于接收和发送本地输入/输出线的信号的全局输入/输出线。 半导体存储器件还包括用于响应于预定控制信号将本地输入/输出线的信号发送到全局输入/输出线的开关装置。 在感测放大器和子字线驱动器之间的交叉区域中形成连接区域。 特别地，切换装置被分离并布置在本地输入/输出线与全局输入/输出线相交的连接区域中。 用于驱动读出放大器的P驱动器和N驱动器以相同的结合布置。