公开(公告)号：US20240303155A1

公开(公告)日：2024-09-12

申请号：US18596818

申请日：2024-03-06

Applicant: MOREH CORP.

Inventor： Gangwon Jo ,  Jungho Park

IPC: G06F11/07

CPC classification number: G06F11/0793

Abstract: Provided is a fault tolerance method which is performed by one or more processors, and which includes receiving an application execute command, executing a main process of an application in response to the execute command, receiving, by a split execution module, information on a plurality of devices associated with the execution of the application from an orchestrator, executing, by the split execution module, a sub-process for each of the plurality of devices using the information on the plurality of devices, and performing, by the split execution module, fault tolerance associated with the execution of the application using an idle device, if a failure occurs in at least some of the plurality of devices.

公开(公告)号：US20240303125A1

公开(公告)日：2024-09-12

申请号：US18418994

申请日：2024-01-22

Applicant: MOREH CORP.

Inventor： Gangwon Jo ,  Jungho Park

IPC: G06F9/50 ,  G06F11/34

CPC classification number: G06F9/5038 ,  G06F11/3466

Abstract: Provided is a method for creating an operation call list for artificial intelligence calculation, which is performed by one or more processors, and includes acquiring a trace from a source program including an artificial intelligence calculation, wherein the trace includes at least one of code or primitive operation associated with the source program, and creating a call list including a plurality of primitive operations based on the trace, in which the plurality of primitive operations may be included in an operation library accessible to each of the plurality of accelerators.

公开(公告)号：US20240303083A1

公开(公告)日：2024-09-12

申请号：US18423642

申请日：2024-01-26

Applicant: MOREH CORP.

Inventor： Gangwon Jo ,  Jungho Park

IPC: G06F9/38

CPC classification number: G06F9/3836

Abstract: A method for compiling for overlapping instructions between a plurality of processors is provided, which is performed by one or more processors, and includes receiving a source program, determining a plurality of instructions to be executed in the plurality of processors based on the source program, and assigning the plurality of instructions to the plurality of processors such that a first portion of the plurality of instructions and a second portion of the plurality of instructions are processed in parallel by each of the plurality of processors.

公开(公告)号：US20240303054A1

公开(公告)日：2024-09-12

申请号：US18426983

申请日：2024-01-30

Applicant: MOREH CORP.

Inventor： Gangwon Jo ,  Jungho Park

IPC: G06F8/41

CPC classification number: G06F8/4434

Abstract: A method for compilation optimization using activation recalculation is provided, which is performed by one or more processors, and includes receiving a source program, determining an operation to be executed in a processor based on the source program, and determining whether or not the operation to be executed corresponds to the operation for activation recalculation, thereby automatically classifying the operation to be executed into a first operation type corresponding to the operation for activation recalculation or a second operation type not corresponding to the operation for activation recalculation.