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37 条记录 (耗时 0.023 秒)

    Transmission gate including body effect compensation circuit
    11.
    发明授权
    Transmission gate including body effect compensation circuit 失效
    传输门包括体效应补偿电路

    公开(公告)号：US6020778A

    公开(公告)日：2000-02-01

    申请号：US64814

    申请日：1998-04-23

    申请人： Hiroshi Shigehara ,  Masanori Kinugasa ,  Toshinobu Hisamoto

    发明人： Hiroshi Shigehara ,  Masanori Kinugasa ,  Toshinobu Hisamoto

    IPC分类号： H03K19/0944 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687

    CPC分类号： H03K17/162 ,  H03K17/063 ,  H03K17/6872 ,  H03K2217/0018

    摘要： Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.

    摘要翻译： 晶体管（P1，N1）中的每一个的两个端子连接在两个端子（A，B）之间。 配置晶体管（P1）的体效应补偿电路（COMP-P1）和晶体管（N1）的体效应补偿电路（COMP-N1）。 电路（COMP-P1）中的晶体管（P1P，P2P）的背栅和电路（COMP-N1）中的晶体管（P1N，P2N）共同连接到晶体管（P1）的背栅极。 电路（COMP-N1）中的晶体管（N1N，N2N）的背栅和电路（COMP-P1）中的晶体管（N1P，N2P）共同连接到晶体管（N1）的背栅极。 利用这种结构，在将信号从一个端子（A或B）传送到另一个端子（B或A）或反之后，信号电位以高速传输到晶体管（P1，N1）的背栅极 以增加信号传输速度。

    Interface circuit with backgate bias control of a transistor
    13.
    发明授权
    Interface circuit with backgate bias control of a transistor 失效
    具有背栅偏置控制的晶体管接口电路

    公开(公告)号：US5442307A

    公开(公告)日：1995-08-15

    申请号：US226683

    申请日：1994-04-12

    申请人： Hiroshi Shigehara ,  Masanori Kinugasa

    发明人： Hiroshi Shigehara ,  Masanori Kinugasa

    IPC分类号： H03K19/0175 ,  H03K19/0185

    CPC分类号： H03K19/018507 ,  H03K19/018521 ,  H03K2217/0018

    摘要： An interface circuit includes first and second MOS transistors of depletion type, first and second switching elements, and a control circuit. The current path of the first MOS transistor is connected between an output node of a MOS circuit formed in a semiconductor substrate and an output terminal and the gate thereof is connected to a power supply. The first switching element is connected between the backgate of the first MOS transistor and a ground terminal. The second switching element and the current path of the second MOS transistor are serially connected between the backgate of the first MOS transistor and the output terminal. The gate of the second MOS transistor is connected to the power supply and the backgate thereof is connected to the backgate of the first MOS transistor. The first and second switching elements are set into complementary states according to an output of the MOS circuit in response to an output signal of the control circuit.

    摘要翻译： 接口电路包括耗尽型，第一和第二开关元件的第一和第二MOS晶体管和控制电路。 第一MOS晶体管的电流路径连接在形成在半导体衬底中的MOS电路的输出节点和输出端子之间，并且其栅极连接到电源。 第一开关元件连接在第一MOS晶体管的背栅和接地端子之间。 第二开关元件和第二MOS晶体管的电流路径串联连接在第一MOS晶体管的背栅和输出端之间。 第二MOS晶体管的栅极连接到电源，并且其背栅极连接到第一MOS晶体管的背栅。 响应于控制电路的输出信号，第一和第二开关元件根据MOS电路的输出设置为互补状态。

    Output circuit of an integrated circuit having immunity to power source fluctuations
    14.
    发明授权
    Output circuit of an integrated circuit having immunity to power source fluctuations 失效
    具有对电源波动的抗扰性的集成电路的输出电路

    公开(公告)号：US5220205A

    公开(公告)日：1993-06-15

    申请号：US808921

    申请日：1991-12-18

    申请人： Hiroshi Shigehara ,  Masanori Kinugasa

    发明人： Hiroshi Shigehara ,  Masanori Kinugasa

    IPC分类号： H03K5/1252 ,  H03K3/013 ,  H03K3/356 ,  H03K17/16

    CPC分类号： H03K3/356165 ,  H03K3/013

    摘要： A series circuit of two P-channel transistors and a series circuit of two N-channel transistors are used respectively as a latch circuit which temporarily latches an input signal until the power source fluctuation caused by the change of the output signal is suppressed. The gates of the transistors of the two series-circuits are supplied with the output signal of an output-stage circuit and a delayed output signal obtained by delaying the above output signal so that either one of the two series-circuits can be controlled to be turned on so as to temporarily latch an input signal in a dynamic manner until the power source fluctuation is suppressed. Since the gate signals to the transistors of the two series-circuits are directly supplied without being passed through single-channel type transfer gates, a sufficiently large bias voltages are supplied to the gate of the latch circuits even under the low power source voltage. Thus, the output circuit capable of providing a desired operation characteristic even under the low operation voltage can be realized.

    摘要翻译： 分别使用两个P沟道晶体管的串联电路和两个N沟道晶体管的串联电路作为暂时锁存输入信号的锁存电路，直到由输出信号的变化引起的电源波动被抑制。 两个串联电路的晶体管的栅极被提供有输出级电路的输出信号和通过延迟上述输出信号而获得的延迟输出信号，使得两个串联电路中的任一个可被控制为 导通，以便以动态方式临时锁存输入信号，直到电源波动被抑制为止。 由于两个串联电路的晶体管的栅极信号被直接提供而不通过单通道型传输门，所以即使在低功率源电压下也能将足够大的偏置电压提供给锁存电路的栅极。 因此，能够实现即使在低工作电压下也能够提供期望的动作特性的输出电路。

    MOS type input circuit
    15.
    发明授权
    MOS type input circuit 失效
    MOS型输入电路

    公开(公告)号：US5175445A

    公开(公告)日：1992-12-29

    申请号：US691414

    申请日：1991-04-25

    申请人： Masanori Kinugasa ,  Hiroshi Shigehara

    发明人： Masanori Kinugasa ,  Hiroshi Shigehara

    IPC分类号： H03K3/353 ,  H03K3/3565 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/0948

    CPC分类号： H03K3/3565 ,  H03K19/00384 ,  H03K19/0948

    摘要： The source-drain paths of p-channel first and second MOSFETs are connected in series between a node, to which a high-potential power source voltage is supplied, and a signal output node. The source-drain paths of n-channel third and fourth MOSFETs are connected in series between the signal output node and a node to which a low-potential power source voltage is supplied. A signal from an input node is supplied to the gates of said four MOSFETs in a parallel manner. The source-drain path of an n-channel fifth MOSFET is connected in parallel to the source-drain path of the second MOSFET which is not directly connected to the node of the high-potential power source voltage. The gate of the fifth MOSFET is connected to the node of the high-potential power source voltage. The source-drain path of a p-channel sixth MOSFET is connected in parallel to the source-drain path of the third MOSFET which is not directly connected to the node of the low-potential power source voltage. The gate of the sixth MOSFET is connected to the node of the low-potential power source voltage.

    Transmission gate
    18.
    发明授权
    Transmission gate 失效

    公开(公告)号：US06335653B1

    公开(公告)日：2002-01-01

    申请号：US09699488

    申请日：2000-10-31

    申请人： Hiroshi Shigehara ,  Masanori Kinugasa ,  Toshinobu Hisamoto

    发明人： Hiroshi Shigehara ,  Masanori Kinugasa ,  Toshinobu Hisamoto

    IPC分类号： H03K301

    CPC分类号： H03K17/162 ,  H03K17/063 ,  H03K17/6872 ,  H03K2217/0018

    摘要： Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.

    MOS output buffer with overvoltage protection circuitry
    19.
    发明授权
    MOS output buffer with overvoltage protection circuitry 失效
    MOS输出缓冲器带过压保护电路

    公开(公告)号：US5880603A

    公开(公告)日：1999-03-09

    申请号：US657599

    申请日：1996-05-31

    申请人： Hiroshi Shigehara ,  Masanori Kinugasa

    发明人： Hiroshi Shigehara ,  Masanori Kinugasa

    IPC分类号： H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0948

    CPC分类号： H03K19/00315

    摘要： Either a power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to an output terminal while the power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to a pn-junction provided between the drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.

    摘要翻译： 电源电位或接地电位通过开关施加到电源节点。 当在电源节点连接到接地电位节点的同时将高于接地电位的电位施加到输出端子时，结合在输出部分中的第一PMOS晶体管的背栅极的电位根据 由于设置在第一PMOS晶体管的漏极和背栅之间的pn结，输出端子的电位。 此时，源极 - 漏极路径连接在第一PMOS晶体管的背栅极和栅极之间的第二PMOS晶体管导通，由此第一PMOS晶体管的背栅极的电位被传送到其栅极。

    Protection circuit for semiconductor devices
    20.
    发明授权
    Protection circuit for semiconductor devices 失效
    半导体器件保护电路

    公开(公告)号：US5821797A

    公开(公告)日：1998-10-13

    申请号：US623838

    申请日：1996-03-29

    申请人： Masanori Kinugasa ,  Ryuji Fujiwara

    发明人： Masanori Kinugasa ,  Ryuji Fujiwara

    IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L23/58 ,  H01L27/02 ,  H01L27/088 ,  H03K17/16

    CPC分类号： H01L27/0251

    摘要： A protection circuit (1) for input comprises two transistors (11, 12) connected in series between a first voltage supply (V.sub.cc) and a second voltage supply (GND), and an intermediate junction point is used as an input terminal and an output terminal. When a surge voltage is applied to the input terminal, since terminals (51, 53) of the two transistors (11, 12) are connected to predetermined junction points in such a way that the transistors can operate as bipolar transistors or cause punch through phenomenon (without causing breakdown operation of a low response speed to surge voltage), the surge voltage can be absorbed at high speed, thus increasing anti-ESD (electro static discharge) rate. Further, a protection circuit for power supply comprises two transistors (31, 32) connected in parallel to each other between a first voltage supply (V.sub.cc) and a second voltage supply (GND). Similarly, the terminals (65, 68) of the two transistors are connected to predetermined junction points in such a way that when a surge voltage is superimposed upon the supply voltage, at least one of the transistors can operate as a bipolar transistor, without causing breakdown operation.

    摘要翻译： 用于输入的保护电路（1）包括串联连接在第一电压源（Vcc）和第二电压源（GND）之间的两个晶体管（11,12），并且中间连接点用作输入端子和输出端 终奌站。 当浪涌电压施加到输入端时，由于两个晶体管（11,12）的端子（51,53）连接到预定的连接点，晶体管可以作为双极晶体管工作或引起冲击现象 （不引起低响应速度对浪涌电压的击穿操作），浪涌电压可以高速吸收，从而增加抗静电（静电放电）率。 此外，用于电源的保护电路包括在第一电压源（Vcc）和第二电压源（GND）之间并联连接的两个晶体管（31,32）。 类似地，两个晶体管的端子（65,68）以这样的方式连接到预定的接合点，使得当浪涌电压叠加在电源电压上时，至少一个晶体管可以作为双极晶体管工作，而不会引起 击穿操作。