公开(公告)号：US07521308B2

公开(公告)日：2009-04-21

申请号：US11616147

申请日：2006-12-26

申请人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

发明人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/31604 ,  H01L29/66575

摘要： A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.

摘要翻译： 制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。 栅极结构和导体区域构成晶体管。 为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。 在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。 第二功率电平比第一功率电平高（例如，至少高5倍）。

公开(公告)号：US20100078687A1

公开(公告)日：2010-04-01

申请号：US12242078

申请日：2008-09-30

申请人： Da Zhang ,  Voon-Yew Thean ,  Christopher V. Baiocco ,  Jie Chen ,  Weipeng Li ,  Young Way Teh ,  Jin Wallner

发明人： Da Zhang ,  Voon-Yew Thean ,  Christopher V. Baiocco ,  Jie Chen ,  Weipeng Li ,  Young Way Teh ,  Jin Wallner

IPC分类号： H01L21/8238 ,  H01L29/04

CPC分类号： H01L21/823807 ,  H01L29/045 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/7843

摘要： A semiconductor process and apparatus includes forming channel orientation CMOS transistors (24, 34) with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer (51) over the PMOS and NMOS gate structures, etching the tensile etch stop layer (51) to form tensile sidewall spacers (62) on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer (72) over the NMOS and PMOS gate structures (26, 36) and the tensile sidewall spacers (62). In other embodiments, a first hydrogen-rich etch stop layer (81) is deposited and etched to form sidewall spacers (92) on the exposed gate sidewalls, and then a second tensile etch stop layer (94) is deposited over the NMOS and PMOS gate structures (26, 36) and the sidewall spacers (92).

摘要翻译： 一种半导体工艺和设备包括在NMOS沟道区中形成具有增强的空穴迁移率的<100>沟道定向CMOS晶体管（24,34），并且通过在PMOS区上沉积第一拉伸蚀刻停止层（51），减小PMOS区域中的沟道缺陷率 蚀刻所述拉伸蚀刻停止层（51）以在所述暴露的栅极侧壁上形成拉伸侧壁间隔物（62），然后在所述NMOS和PMOS栅极上沉积第二富氢压缩或中性蚀刻停止层（72） 结构（26,36）和拉伸侧壁间隔物（62）。 在其它实施例中，沉积并蚀刻第一富氢蚀刻停止层（81）以在暴露的栅极侧壁上形成侧壁间隔物（92），然后在NMOS和PMOS上沉积第二拉伸蚀刻停止层（94） 栅极结构（26,36）和侧壁间隔物（92）。

公开(公告)号：US07471548B2

公开(公告)日：2008-12-30

申请号：US11611569

申请日：2006-12-15

申请人： Christopher V. Baiocco ,  Xiangdong Chen ,  Young G. Ko ,  Melanie J. Sherony

发明人： Christopher V. Baiocco ,  Xiangdong Chen ,  Young G. Ko ,  Melanie J. Sherony

IPC分类号： G11C11/412 ,  H01L29/78

CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903

摘要： An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. The gamma ratio is increased with degraded pFET device performance. Morever, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides an integrated circuit (IC) that comprises at least one SRAM cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the nFET and the pFET.

摘要翻译： 提供了一种集成电路（IC），其包括至少一个静态随机存取存储器（SRAM）单元，其中提高了SRAM单元的性能，但具有良好的稳定性和可写性。 特别地，本发明提供一种包括至少一个SRAM单元的IC，其中伽马比为约1或更大。 γ比值随着pFET器件性能的降低而增加。 更重要的是，在本发明的IC中，在SRAM区域中不存在应力衬垫边界，并且与常规SRAM结构相比，所有器件的离子变化都减小了。 本发明提供一种集成电路（IC），其包括至少一个包含至少一个nFET和至少一个pFET的SRAM单元; 以及位于nFET和pFET上方并与其相邻的连续松弛应力衬垫。

公开(公告)号：US20080142895A1

公开(公告)日：2008-06-19

申请号：US11611569

申请日：2006-12-15

申请人： Christopher V. Baiocco ,  Xiangdong Chen ,  Young G. Ko ,  Melanie J. Sherony

发明人： Christopher V. Baiocco ,  Xiangdong Chen ,  Young G. Ko ,  Melanie J. Sherony

IPC分类号： H01L27/11

CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903

摘要： An IC is provided that includes at least one SRAM cell in which the performance of the SRAM cell is enhanced, yet maintaining good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention, solves the above by providing an integrated circuit (IC) that comprises at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET.

摘要翻译： 提供了一种IC，其包括至少一个SRAM单元，其中SRAM单元的性能得到增强，同时保持良好的稳定性和可编写性。 特别地，本发明提供一种包括至少一个SRAM单元的IC，其中伽马比为约1或更大。 在本发明中，γ比随着pFET器件性能的降低而增加。 此外，在本发明的IC中，在SRAM区域中不存在应力衬垫边界，并且与常规SRAM结构相比，所有器件的离子变化都减小了。 本发明通过提供一种包括至少一个包括至少一个nFET和至少一个pFET的静态随机存取存储器的集成电路（IC）来解决上述问题， 以及位于所述至少一个nFET和所述至少一个pFET之上并邻接所述至少一个nFET的连续松弛应力衬垫。

公开(公告)号：US07081397B2

公开(公告)日：2006-07-25

申请号：US10929990

申请日：2004-08-30

申请人： Christopher V. Baiocco ,  An L. Steegen ,  Ying Zhang

发明人： Christopher V. Baiocco ,  An L. Steegen ,  Ying Zhang

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant region (LIR) in the substrate. Strip the LIM exposing the top surface of the substrate. Form an epitaxial silicon layer over the top surface of the substrate burying the LIR. Form a trench mask over the epitaxial layer. Etch a trench reaching through the epitaxial layer and the LIR. Form oxidized trench sidewalls, an oxidized trench bottom and oxidized sidewalls of the LIR. Etch the oxidized sidewalls of the LIR until the LIR is exposed. Form laterally extending trenches by etching away the LIR.

摘要翻译： 通过以下步骤形成半导体衬底中的横向沟槽。 在半导体衬底的顶表面上形成横向植入掩模（LIM）。 通过LIM将重掺杂浓度植入到衬底中，以在衬底中形成横向植入区域（LIR）。 剥离LIM暴露衬底的顶部表面。 在掩埋LIR的衬底的顶表面上形成外延硅层。 在外延层上形成沟槽掩模。 蚀刻穿过外延层和LIR的沟槽。 形成氧化的沟槽侧壁，氧化沟槽底部和LIR的氧化侧壁。 蚀刻LIR的氧化侧壁，直到LIR暴露。 通过蚀刻掉LIR形成横向延伸的沟槽。