公开(公告)号：US20220366943A1

公开(公告)日：2022-11-17

申请号：US17873911

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Hiroshi Akamatsu ,  Kwang-Ho Cho

IPC: G11C5/14 ,  G06F11/08 ,  G06F3/06

Abstract: Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.

公开(公告)号：US11423953B2

公开(公告)日：2022-08-23

申请号：US16885912

申请日：2020-05-28

Applicant: Micron Technology, Inc.

Inventor： Hiroshi Akamatsu ,  Kwang-Ho Cho

IPC: G11C16/04 ,  G11C5/14 ,  G06F11/08 ,  G06F3/06

Abstract: Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. The row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. The error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.

公开(公告)号：US20210375332A1

公开(公告)日：2021-12-02

申请号：US16885912

申请日：2020-05-28

Applicant: Micron Technology, Inc.

Inventor： Hiroshi Akamatsu ,  Kwang-Ho Cho

IPC: G11C5/14 ,  G06F3/06 ,  G06F11/08

Abstract: Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. For example, the error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.