公开(公告)号：US11354066B2

公开(公告)日：2022-06-07

申请号：US16915889

申请日：2020-06-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shinji Bessho ,  Takuya Nakanishi

IPC: G06F3/06 ,  G11C11/4076

Abstract: Disclosed herein is an apparatus that includes a command shifter configured to receive a command pulse and generate a plurality of first command shifted pulses in parallel, wherein each of the plurality of first command shifted pulses has the same width as the command pulse and the plurality of first command shifted pulses have different phases from each other, and a command filter configured to determine if a plurality of second command shifted pulses are generated correspondingly to the plurality of first command shifted pulses or not generated responsive to pulse overlapping among at least ones of the plurality of first command shifted pulses.

公开(公告)号：US20210405923A1

公开(公告)日：2021-12-30

申请号：US16915889

申请日：2020-06-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shinji Bessho ,  Takuya Nakanishi

IPC: G06F3/06 ,  G11C11/4076

Abstract: Disclosed herein is an apparatus that includes a command shifter configured to receive a command pulse and generate a plurality of first command shifted pulses in parallel, wherein each of the plurality of first command shifted pulses has the same width as the command pulse and the plurality of first command shifted pulses have different phases from each other, and a command filter configured to determine if a plurality of second command shifted pulses are generated correspondingly to the plurality of first command shifted pulses or not generated responsive to pulse overlapping among at least ones of the plurality of first command shifted pulses.

公开(公告)号：US11011218B2

公开(公告)日：2021-05-18

申请号：US16890529

申请日：2020-06-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shinji Bessho ,  Toru Ishikawa ,  Takuya Nakanishi

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4076

Abstract: A system for refresh operations including multiple refresh activations, and a method and an apparatus therefore, are described. The system includes, for example, a memory array; a command address input circuit configured to provide a command for a per bank refresh operation or an all-bank refresh operation, a command control circuit configured to receive the command, and provide first and second internal control signals; a refresh control circuit configured to provide a first refresh control signal; and a row control circuit configured to provide a second refresh control signal. The provided first internal control signal is based on the provided command. For the per bank refresh operation, the provided second internal control signal is based on the second refresh control signal, and, for the all-bank refresh operation, the provided second internal control signal is based on the first internal control signal delayed by the command control circuit.