公开(公告)号：US06173354B2

公开(公告)日：2001-01-09

申请号：US09205255

申请日：1998-12-04

申请人： Narendra Khandekar ,  Zohar Bogin ,  Steve Clohset

发明人： Narendra Khandekar ,  Zohar Bogin ,  Steve Clohset

IPC分类号： G06F1300

CPC分类号： G06F13/4031

摘要： A method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus is described. In one embodiment, the method includes detecting a write cycle by an initiator for transmitting data to a device. The method further includes asserting a write request to the device, responsive to detecting the write cycle, asserting a ready request to the initiator without detecting an acknowledge from the device, and receiving the data from the initiator.

摘要翻译： 描述了用于将总线桥的内部延迟与外部总线上的内部延迟相分离的方法和装置。 在一个实施例中，该方法包括检测由发起者发送数据到设备的写周期。 所述方法还包括：响应于检测到所述写周期来向所述设备发出写入请求，向所述发起者断言准备好的请求，而不检测来自所述设备的确认，以及从所述发起者接收所述数据。

公开(公告)号：US6049887A

公开(公告)日：2000-04-11

申请号：US985390

申请日：1997-12-04

申请人： Narendra Khandekar ,  Ashish S. Gadagkar ,  Robert F. Kubick ,  Vincent E. VonBokern ,  Manish Muthal

发明人： Narendra Khandekar ,  Ashish S. Gadagkar ,  Robert F. Kubick ,  Vincent E. VonBokern ,  Manish Muthal

IPC分类号： G06F1/10 ,  G06F11/00

CPC分类号： G06F1/10

摘要： A method of transmitting a signal from a first clock domain to a second clock domain commences with the generation of first and second clock signals. The first and second clock signals are substantially synchronous and have respective frequencies that are non-integer multiples. A first signal, which is generated in the first clock domain responsive to a transition of the first clock signal that is substantially coincident with a transition of the second clock signal, is prevented from being latched in the second clock domain responsive to the transition of the second clock signal. The first clock signal is prevented from being latched for a time period which is greater than a maximum clock skew which may exist between the first and second clock signals.

摘要翻译： 将信号从第一时钟域发送到第二时钟域的方法从产生第一和第二时钟信号开始。 第一和第二时钟信号基本上是同步的并且具有非整数倍的相应频率。 响应于基本上与第二时钟信号的转换相关的第一时钟信号的转变而在第一时钟域中产生的第一信号被防止被锁存在第二时钟域中， 第二个时钟信号。 防止第一时钟信号被锁存大于可能存在于第一和第二时钟信号之间的最大时钟偏移的时间段。

公开(公告)号：US5715476A

公开(公告)日：1998-02-03

申请号：US580748

申请日：1995-12-29

申请人： Aniruddha Kundu ,  Narendra Khandekar

发明人： Aniruddha Kundu ,  Narendra Khandekar

IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F13/28 ,  G06F15/40

CPC分类号： G06F13/28

摘要： Memory access control logic for controlling sequential and toggle mode burst accesses to a memory in a computer system using toggle mode automatic increment logic. The memory access control logic of the invention controls the sequence in which locations of a memory are accessed during a memory burst access operation wherein the burst access sequence is determined by an order in which a burst access starting address is incremented. Toggle increment logic for incrementing a starting address in a toggle sequence is included in the computer system in which the memory access control logic of the invention is used. An input bus receives a burst access request and a burst access starting address indicating a first memory location to be accessed in response to the burst access request from a device in the computer system. Additional logic determines whether the device requires a linear increment sequence or a toggle increment sequence for the burst access. Control logic controls the toggle increment logic to increment the starting address in a linear sequence in response to determining that the first device requires a linear increment sequence.

摘要翻译： 存储器访问控制逻辑，用于使用切换模式自动增量逻辑来控制对计算机系统中的存储器的顺序和切换模式突发访问。 本发明的存储器访问控制逻辑控制在存储器突发存取操作期间访问存储器的位置的序列，其中脉冲串存取序列由突发存取开始地址增加的顺序确定。 在使用本发明的存储器访问控制逻辑的计算机系统中包括用于递增开关序列中的起始地址的切换递增逻辑。 输入总线响应于来自计算机系统中的设备的突发接入请求，接收突发接入请求和突发接入起始地址，指示要接入的第一存储器位置。 附加逻辑决定了设备是否需要线性增量序列或突发访问的切换增量序列。 响应于确定第一设备需要线性增量序列，控制逻辑控制切换增量逻辑以线性序列递增起始地址。