SMART CACHE CONTROL FOR MISSION-CRITICAL AND HIGH PRIORITY TRAFFIC FLOWS

    公开(公告)号:US20220247690A1

    公开(公告)日:2022-08-04

    申请号:US17165362

    申请日:2021-02-02

    Abstract: A system, apparatus, method, and non-transitory computer readable medium for providing smart cache control for mission-critical and high-priority traffic flows may include a network device which is caused to, extract attributes from a network packet, determine whether to request a new flow rule from a network controller for the network packet based on the extracted attributes, transmit a new flow rule request to the network controller based on results of the determining, the new flow rule request including the extracted attributes, receive the new flow rule from the network controller in response to the new flow rule request, and store the new flow rule in at least one cache memory based on priority information of the new flow rule.

    DEDICATED MEMORY BUFFERS FOR SUPPORTING DETERMINISTIC INTER-FPGA COMMUNICATION

    公开(公告)号:US20210406178A1

    公开(公告)日:2021-12-30

    申请号:US16911680

    申请日:2020-06-25

    Abstract: A server includes a field programmable gate array (FPGA) partitioned into a set of partial reconfiguration (PR) slots and a memory that supports a set of logical buffers. A deterministic application request module (DARM) receives application requests to allocate the set of reconfiguration slots to one or more tenants and the one or more tenants configure the allocated reconfiguration slot to perform tasks. The DARM stores data associated with the application request in a first logical buffer from the set of logical buffers. A reconfiguration slot scheduling (RSS) module identifies a first reconfiguration slot from the set of reconfiguration slots and associates the first reconfiguration slot with the first logical buffer. A reconfiguration slot initialization (RSI) module reconfigures the first reconfiguration slot to perform the tasks based on the data stored in the first logical buffer.

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