公开(公告)号：US20080275686A1

公开(公告)日：2008-11-06

申请号：US11742929

申请日：2007-05-01

申请人： Timothy John Mullins ,  Roy Glenn Musselman ,  Yuan-Ping Pang ,  Kurt Walter Pinnow ,  Brian Paul Wallenfelt

发明人： Timothy John Mullins ,  Roy Glenn Musselman ,  Yuan-Ping Pang ,  Kurt Walter Pinnow ,  Brian Paul Wallenfelt

IPC分类号： G06G7/48

CPC分类号： G16C10/00

摘要： A technique for reducing the number of actions performed as part of a molecular modeling simulation is disclosed. For example, embodiments of the invention may be used to reduce the number of comparisons performed in a simulation of binding affinity between a first molecule (e.g., a protein receptor site) and a second molecule (e.g., a ligand). Because such a simulation is typically performed a very large number of times for even one particular first and second molecule, and is further performed for different combinations of first and second molecules, the effect of reducing the number of comparisons is leveraged and can provide a significant impact on overall simulation performance.

摘要翻译： 公开了一种用于减少作为分子模拟模拟的一部分而执行的动作数量的技术。 例如，本发明的实施方案可以用于减少在第一分子（例如，蛋白质受体位点）和第二分子（例如配体）之间的结合亲和力的模拟中进行的比较的数量。 因为这样的模拟通常对于甚至一个特定的第一和第二分子进行非常多的次数，并且对于第一和第二分子的不同组合进一步进行，所以可以利用减少比较数量的效果并且可以提供显着的 影响整体模拟性能。

公开(公告)号：US07096470B2

公开(公告)日：2006-08-22

申请号：US10246912

申请日：2002-09-19

申请人： Jeffrey Douglas Brown ,  Harold F. Kossman ,  Timothy John Mullins

发明人： Jeffrey Douglas Brown ,  Harold F. Kossman ,  Timothy John Mullins

IPC分类号： G06F9/46 ,  G06F15/00

CPC分类号： G06F9/3851 ,  G06F9/4881 ,  G06F2209/483

摘要： A method and apparatus are provided for implementing thread replacement for optimal performance in a two-tiered multithreading structure. A first tier thread state storage stores a limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. Each stored thread state includes predefined selection data. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, uses the stored predefined selection data for selectively exchanging thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.

摘要翻译： 提供了一种用于在双层多线程结构中实现线程替换以获得最佳性能的方法和装置。 第一层线程状态存储器存储有限数量的可运行线程寄存器状态。 第二层线程存储设备存储大于有限数量的可运行线程寄存器状态的第二数量的线程状态。 每个存储的线程状态包括预定义的选择数据。 耦合在第一层线程状态存储器和第二层级线程存储设备之间的可运行线程选择逻辑使用存储的预定义选择数据来选择性地交换第一层有限数量的可运行线程寄存器状态和第二层线程存储设备之间的线程状态 。

公开(公告)号：US6049867A

公开(公告)日：2000-04-11

申请号：US906228

申请日：1997-08-04

申请人： Richard James Eickemeyer ,  Ross Evan Johnson ,  Harold F. Kossman ,  Steven Raymond Kunkel ,  Timothy John Mullins ,  James Allen Rose

发明人： Richard James Eickemeyer ,  Ross Evan Johnson ,  Harold F. Kossman ,  Steven Raymond Kunkel ,  Timothy John Mullins ,  James Allen Rose

IPC分类号： G06F9/38 ,  G06F9/48 ,  G06F12/08

CPC分类号： G06F9/4881 ,  G06F12/0811 ,  G06F12/0842 ,  G06F9/3851

摘要： A method and system for enhanced performance multithread operation in a data processing system which includes a processor, a main memory store and at least two levels of cache memory. At least one instruction within an initial thread is executed. Thereafter, the state of the processor at a selected point within the first thread is stored, execution of the first thread is terminated and a second thread is selected for execution only in response to a level two or higher cache miss, thereby minimizing processor delays due to memory latency. The validity state of each thread is preferably maintained in order to minimize the likelihood of returning to a prior thread for execution before the cache miss has been corrected. A least recently executed thread is preferably selected for execution in the event of a nonvalidity indication in association with all remaining threads, in anticipation of a change to the valid status of that thread prior to all other threads. A thread switch bit may also be utilized to selectively inhibit thread switching where execution of a particular thread is deemed necessary.

摘要翻译： 一种用于在数据处理系统中增强性能多线程操作的方法和系统，其包括处理器，主存储器存储器和至少两个级别的高速缓冲存储器。 执行初始线程内的至少一条指令。 此后，存储处于第一线程内的选定点的处理器的状态，终止第一线程的执行，并且仅响应于二级或更高级别的高速缓存未命中而选择执行第二线程，从而最小化处理器延迟 到内存延迟。 优选地保持每个线程的有效性状态，以便在高速缓存未命中被校正之前最小化返回到先前线程执行的可能性。 在所有其他线程之前，对于线程的有效状态的改变，优选地，在与所有剩余线程相关联的非有效性指示的情况下，选择最不执行的线程用于执行。 线程切换位也可用于选择性地禁止线程切换，其中特定线程的执行被认为是必要的。