-
公开(公告)号：US20120050554A1
公开(公告)日：2012-03-01
申请号：US13215799
申请日：2011-08-23
申请人： Peter Alan Levine , Rui Zhu , John Robertson Tower
发明人： Peter Alan Levine , Rui Zhu , John Robertson Tower
IPC分类号： H04N5/225
CPC分类号： H04N5/33 , H01L27/14609 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H04N5/374
摘要： A pixel design is disclosed. The pixel includes a photo-sensitive element. A first reflective layer substantially overlies the photo-sensitive element. A second reflective layer substantially underlies the photo-sensitive element and forms a cavity with the first reflective layer that is non-resonant with respect to photon absorption. An aperture is formed in either the first reflective layer or the second reflective layer. When electromagnetic radiation enters the aperture, the first reflective layer and the second reflective layer are configured to reflect the electromagnetic radiation substantially toward each other until substantially absorbed in the cavity.
摘要翻译： 公开了像素设计。 像素包括光敏元件。 基本上覆盖光敏元件的第一反射层。 第二反射层基本上位于感光元件下面，并且形成与第一反射层相对于光子吸收不共振的空腔。 在第一反射层或第二反射层中形成孔。 当电磁辐射进入孔径时，第一反射层和第二反射层构造成基本上彼此相对地反射电磁辐射，直到基本上被吸收在空腔中。
-
公开(公告)号：US07948536B2
公开(公告)日：2011-05-24
申请号：US12128890
申请日：2008-05-29
CPC分类号： H04N5/365 , H01L27/14609 , H01L27/14643 , H04N5/369
摘要： A method and apparatus for equalizing gain in an array of electron multiplication (EM) pixels is disclosed, each pixel having one or more impact ionization gain stages with implants to achieve charge transfer directionality and comprising a phase 1 clocked gate, an EM clocked gate, and two DC gates formed between the phase 1 clocked gate and the EM clocked gate, comprising the steps of (a) applying initial voltages to each of the DC gates and the EM clocked gates of at least two pixels of a plurality of pixels; (b) clocking phase 1 clock gates and an EM clock gates associated with the at least two pixels of the plurality of pixels a predetermined number of times to achieve an average pixel intensity value after impact ionization gain; and (c) selectively adjusting the difference in voltage between the DC gate and corresponding EM clocked gate of the at least two pixels of the plurality of pixels until the difference between the resulting pixel intensity values and the average pixel intensity value needed to produce a desired uniform gain image is below a predetermined threshold.
摘要翻译： 公开了一种用于均衡电子倍增（EM）像素阵列中的增益的方法和装置，每个像素具有一个或多个具有植入物的冲击电离增益级，以实现电荷转移方向性，并且包括相位1时钟门，EM时钟门， 和形成在相位1时钟门和EM时钟门之间的两个DC门，包括以下步骤：（a）向多个像素中的至少两个像素的DC门和EM时钟门中的每一个施加初始电压; （b）将预定次数与所述多个像素中的所述至少两个像素相关联的时钟相位1个时钟门和EM时钟门，以实现冲击电离增益之后的平均像素强度值; 以及（c）选择性地调整所述多个像素中的所述至少两个像素的所述DC栅极与所述对应的EM时钟栅极之间的电压差，直到得到的像素强度值与产生所需的像素强度值所需的平均像素强度值之间的差值 均匀增益图像低于预定阈值。
-
公开(公告)号：US20120056079A1
公开(公告)日：2012-03-08
申请号：US13223991
申请日：2011-09-01
申请人： Peter Alan Levine , Rui Zhu
发明人： Peter Alan Levine , Rui Zhu
IPC分类号： G01J1/42
CPC分类号： H04N5/3592
摘要： A method of operating a CMOS pixel is disclosed. The CMOS pixel includes a photodiode (PPD), a transfer gate coupled to the PPD, and an anti-blooming drain coupled to the transfer gate. A potential barrier is formed between a potential well underlying the PPD and the transfer gate. Charge is accumulated in the potential well in response to electromagnetic radiation during a first integration time. Excess charge is removed from the potential well to the anti-blooming drain that exceeds the first potential barrier. A size of the potential barrier is increased. Charge is accumulated in the potential well during a second integration time.
摘要翻译： 公开了一种操作CMOS像素的方法。 CMOS像素包括光电二极管（PPD），耦合到PPD的传输栅极和耦合到传输栅极的抗散花漏极。 在PPD和传输门下方的势阱之间形成势垒。 在第一积分时间期间，响应于电磁辐射，电荷在电位阱中累积。 过量的电荷从潜在的阱移除到超过第一势垒的防开裂漏极。 势垒的大小增加。 在第二次积分时间期间，电荷积聚在势阱中。
-
公开(公告)号：US06535275B2
公开(公告)日：2003-03-18
申请号：US09772361
申请日：2001-01-30
申请人： Nathaniel Joseph McCaffrey , Robert James Andreas , Peter Alan Levine , Ramon Ubaldo Martinelli
发明人： Nathaniel Joseph McCaffrey , Robert James Andreas , Peter Alan Levine , Ramon Ubaldo Martinelli
IPC分类号： G01C308
CPC分类号： G01S17/89 , G01S7/4873 , G01S17/105
摘要： A three-dimensional imaging range finder is disclosed using a transmitted pulse reflected from a target. The range finder includes a pixel sensor for receiving light from the target and the reflected pulse. A global counter is provided for determining a time-of-flight value of the transmitted pulse by providing accurate count data to pixel memories. A processing circuit, which is coupled to the pixel sensor and the global counter, extracts the reflected pulse received by the pixel sensor, and stores the time-of-flight value upon extracting the reflected pulse. The pixel sensor provides a luminance signal and the processing circuit includes a high pass filter to extract the reflected pulse from the luminance signal.
摘要翻译： 公开了使用从目标反射的发射脉冲的三维成像测距仪。 测距仪包括用于接收来自目标的光和反射脉冲的像素传感器。 提供了一个全局计数器，用于通过向像素存储器提供精确的计数数据来确定发射脉冲的飞行时间值。 耦合到像素传感器和全局计数器的处理电路提取由像素传感器接收的反射脉冲，并且在提取反射脉冲时存储飞行时间值。 像素传感器提供亮度信号，并且处理电路包括高通滤波器以从亮度信号中提取反射的脉冲。
-
公开(公告)号：US6040570A
公开(公告)日：2000-03-21
申请号：US87087
申请日：1998-05-29
CPC分类号： H04N5/35527 , H04N3/155
摘要： The invention relates to an extended dynamic range imager. An array of pixels provides an output signal for each pixel related to an amount of light captured for each pixel during an integration period. A row of extended dynamic range (XDR) sample and hold circuits having an XDR sample and hold circuit for each column of the array captures an XDR signal related to a difference between the output signal and an XDR clamp level to which the pixel is reset at a predetermined time before the end of the integration period. A row of linear sample and hold circuits having a linear sample and hold circuit for each column of the array captures a linear signal related to a difference between the output signal and an initial output signal to which the pixel is reset at the beginning of the integration period.
摘要翻译： 本发明涉及一种扩展动态范围成像器。 像素阵列为在整合时段期间针对每个像素捕获的光量的每个像素提供输出信号。 具有用于阵列的每列的XDR采样和保持电路的扩展动态范围（XDR）采样和保持电路行捕获与输出信号和像素被复位的XDR钳位电平之间的差异相关的XDR信号 在积分期结束之前的预定时间。 具有用于阵列的每列的线性采样和保持电路的线性采样和保持电路行捕获与在积分开始时像素被复位的输出信号和初始输出信号之间的差相关的线性信号 期。
-
公开(公告)号：US5844238A
公开(公告)日：1998-12-01
申请号：US622263
申请日：1996-03-27
IPC分类号： C07D405/06 , G01J5/34 , G01J5/40 , G01J5/48 , H04N5/33
CPC分类号： C07D405/06 , G01J5/34 , G01J5/40 , H04N5/33
摘要： An infrared imager includes an array of capacitance sensors that operate at room temperature. Each infrared capacitance sensor includes a deflectable first plate which expands due to absorbed thermal radiation relative to a non-deflectable second plate. In one embodiment each infrared capacitance sensor is composed of a bi-material strip which changes the position of one plate of a sensing capacitor in response to temperature changes due to absorbed incident thermal radiation. The bi-material strip is composed of two materials with a large difference in thermal expansion coefficients.
-
公开(公告)号：US4032976A
公开(公告)日：1977-06-28
申请号：US677755
申请日：1976-04-16
申请人： Peter Alan Levine
发明人： Peter Alan Levine
CPC分类号： H04N3/1568 , H01L27/14887
摘要： Radiation illuminating the A register of a charge-coupled device (CCD) imager of the field transfer type during the transfer of a field from A to the B register results in smear in the reproduced image. Such smear is reduced by removing any charge which may be present in the A register, during a period which begins just after the transfer of a field from the A to the B register, and which terminates when the integration of the next field begins.
-
公开(公告)号：US08946818B2
公开(公告)日：2015-02-03
申请号：US12760895
申请日：2010-04-15
IPC分类号： H01L27/12 , H01L27/146 , H01L27/148 , H01L31/18
CPC分类号： H01L27/14643 , H01L27/1464 , H01L27/148 , H01L31/18 , H01L31/1892 , Y02E10/50
摘要： A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The device includes an insulator layer; a semiconductor substrate, having an interface with the insulator layer; an epitaxial layer grown on the semiconductor substrate by epitaxial growth; and one or more imaging components in the epitaxial layer in proximity to a face of the epitaxial layer, the face being opposite the interface of the semiconductor substrate and the insulator layer, the imaging components comprising junctions within the epitaxial layer; wherein the semiconductor substrate and the epitaxial layer exhibit a net doping concentration having a maximum value at a predetermined distance from the interface of the insulating layer and the semiconductor substrate and which decreases monotonically on both sides of the profile from the maximum value within a portion of the semiconductor substrate and the epitaxial layer. The doping profile between the interface with the insulation layer and the peak of the doping profile functions as a “dead band” to prevent dark current carriers from penetrating to the front side of the device.
摘要翻译： 公开了一种用于在绝缘体上半导体衬底上制造背照式半导体成像器件的方法，以及所得成像器件。 该装置包括绝缘体层; 半导体衬底，与绝缘体层具有界面; 通过外延生长在半导体衬底上生长的外延层; 以及在所述外延层中靠近所述外延层的表面的一个或多个成像组件，所述表面与所述半导体衬底和所述绝缘体层的界面相对，所述成像组件包括所述外延层内的结; 其中所述半导体衬底和所述外延层表现出净绝缘浓度，所述净掺杂浓度在距所述绝缘层和所述半导体衬底的界面预定距离处具有最大值，并且所述净掺杂浓度在所述剖面的两侧上从所述最大值的单一部分 半导体衬底和外延层。 与绝缘层的界面和掺杂分布的峰值之间的掺杂分布用作“死区”，以防止暗电流载流子穿透到器件的前侧。
-
公开(公告)号：US08178914B2
公开(公告)日：2012-05-15
申请号：US12579623
申请日：2009-10-15
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/1464 , H01L27/1214 , H01L27/1266 , H01L27/14645 , H01L27/14683 , H01L2224/48463
摘要： A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate is disclosed. The substrate includes an insulator layer and an epitaxial layer overlying the insulator layer. A bond pad region is formed extending into the epitaxial layer to a surface of the insulator layer. A bond pad is fabricated partially overlying the bond pad region. At least one imaging component is fabricated partially overlying and extending into the epitaxial layer. A passivation layer is fabricated overlying the epitaxial layer, the bond pad, and the at least one imaging component. A handle wafer is bonded to the passivation layer. A portion of the insulator layer and a portion of the bond pad region is etched to expose a portion of the bond pad.
摘要翻译： 公开了一种在绝缘体上半导体衬底上制造背照式半导体成像器件的方法。 衬底包括绝缘体层和覆盖绝缘体层的外延层。 形成延伸到外延层中的接合焊盘区域到绝缘体层的表面。 部分覆盖接合焊盘区域的接合焊盘。 至少一个成像部件被部分地覆盖并延伸到外延层中。 制造覆盖外延层，接合焊盘和至少一个成像部件的钝化层。 处理晶片结合到钝化层。 绝缘体层的一部分和接合焊盘区域的一部分被蚀刻以暴露接合焊盘的一部分。
-
公开(公告)号：US07129975B2
公开(公告)日：2006-10-31
申请号：US10043768
申请日：2002-01-10
IPC分类号： H04N9/64
CPC分类号： H04N5/2176
摘要： A video imaging system includes an imaging array having a plurality of picture elements (pixels) formed in a substrate. An analog to digital converter formed in the substrate converts signals from the pixels into digital pixel signals. A defect detection circuit formed in said substrate provides a defective pixel output signal indicating, as the digital pixel signal corresponding to the pixels is processed, if any one pixel of the plurality of pixels in the imaging array is defective. The video imaging system includes a defect substitution circuit, also formed in the substrate, that substitutes a corrected pixel for any defective pixel. The video imaging system is responsive to a gain control signal to adjusts the pixels in magnitude. The gain control signal is applied to the first circuit to control the analysis of the pixel to determine if it is defective.
-
-
-
-
-
-
-
-
-
搜索结果
40 条记录 (耗时 0.035 秒)