Method for producing a mask for the lithographic projection of a pattern onto a substrate
    11.
    发明授权
    Method for producing a mask for the lithographic projection of a pattern onto a substrate 失效
    用于制造用于将图案的光刻投影到基板上的掩模的方法

    公开(公告)号:US07644389B2

    公开(公告)日:2010-01-05

    申请号:US11668565

    申请日:2007-01-30

    IPC分类号: G06F17/50 G03F1/00 G03C5/00

    CPC分类号: G03F7/70191 G03F1/00

    摘要: A layout is decomposed into partial patterns. An intermediate mask is drawn for each of the partial patterns. The intermediate masks are used in a mask stepper or scanner progressively for projection again into a common pattern on a test mask. A line width distribution LB(x,y) is determined from the test mask or from a test wafer exposed using the mask, and is converted into a distribution of dose corrections. The transmission T(x,y) of the respective intermediate masks is adapted based upon the calculated dose correction. This can be achieved using additional optical elements which are assigned to the intermediate masks and have shading structure elements, or by laser-induced rear-side introduction of shading elements in the quartz substrate of the intermediate masks themselves.

    摘要翻译: 布局被分解为部分图案。 为每个部分图案绘制中间掩模。 中间掩模在掩模步进器或扫描仪中逐渐用于投影到测试掩模上的共同图案中。 从测试掩模或使用掩模曝光的测试晶片确定线宽度分布LB(x,y),并将其转换成剂量校正的分布。 基于所计算的剂量校正来适应各个中间掩模的传输T(x,y)。 这可以使用分配给中间掩模并具有阴影结构元件的附加光学元件,或者通过激光引起的中间掩模本身的石英衬底中的遮光元件的后侧引入来实现。

    Method for transferring a layout of an integrated circuit level to a semiconductor substrate
    13.
    发明申请
    Method for transferring a layout of an integrated circuit level to a semiconductor substrate 审中-公开
    用于将集成电路电平的布局传送到半导体衬底的方法

    公开(公告)号:US20050196689A1

    公开(公告)日:2005-09-08

    申请号:US11071571

    申请日:2005-03-04

    IPC分类号: G03F1/30 G03F7/20 G03F9/00

    CPC分类号: G03F1/30

    摘要: A mask level layout has an arrangement of lines and spaces with the spaces interconnected by a further space. The spaces are alternately acted upon with a phase deviation with respect to the spaces, where a phase edge between spaces acted upon differently arises in the region of the further space. Alternatively, the connecting space within the layout may be filled with dark regions. An additional space is inserted in a second layout representing a further mask of the same mask set. The additional space enables formation of an insulating region on a semiconductor substrate at the location where formation of a continuous isolation trench is not possible due to the phase edges or dark regions within originally connecting spaces of the first mask. The first mask can be embodied as a hybrid mask with structures according to the principle of alternating phase masks with a large process window.

    摘要翻译: 掩模级别布局具有线和空间的布置,空间通过另外的空间互连。 空间交替地以相对于空间的相位偏移地起作用,其中空间之间的相位在另外空间的区域中不同地起作用。 或者,布局中的连接空间可以用黑色区域填充。 在另一个布局中插入一个额外的空间,表示相同掩模集的另一掩码。 附加空间使得能够在由于第一掩模的原始连接空间内的相位边缘或暗区域而不可能形成连续隔离沟槽的位置处在半导体衬底上形成绝缘区域。 第一个掩模可以实现为具有根据具有大工艺窗口的交替相位掩模原理的结构的混合掩模。

    METHOD FOR PRODUCING A MASK FOR THE LITHOGRAPHIC PROJECTION OF A PATTERN ONTO A SUBSTRATE
    15.
    发明申请
    METHOD FOR PRODUCING A MASK FOR THE LITHOGRAPHIC PROJECTION OF A PATTERN ONTO A SUBSTRATE 失效
    用于生成用于将图案投影到基板上的掩模的掩模的方法

    公开(公告)号:US20070196744A1

    公开(公告)日:2007-08-23

    申请号:US11668565

    申请日:2007-01-30

    CPC分类号: G03F7/70191 G03F1/00

    摘要: A layout is decomposed into partial patterns. An intermediate mask is drawn for each of the partial patterns. The intermediate masks are used in a mask stepper or scanner progressively for projection again into a common pattern on a test mask. A line width distribution LB(x,y) is determined from the test mask or from a test wafer exposed using the mask, and is converted into a distribution of dose corrections. The transmission T(x,y) of the respective intermediate masks is adapted based upon the calculated dose correction. This can be achieved using additional optical elements which are assigned to the intermediate masks and have shading structure elements, or by laser-induced rear-side introduction of shading elements in the quartz substrate of the intermediate masks themselves.

    摘要翻译: 布局被分解为部分图案。 为每个部分图案绘制中间掩模。 中间掩模在掩模步进器或扫描仪中逐渐用于投影到测试掩模上的共同图案中。 从测试掩模或使用掩模曝光的测试晶片确定线宽度分布LB(x,y),并将其转换成剂量校正的分布。 基于所计算的剂量校正来适应各个中间掩模的传输T(x,y)。 这可以使用分配给中间掩模并具有阴影结构元件的附加光学元件,或者通过激光引起的中间掩模本身的石英衬底中的遮光元件的后侧引入来实现。

    Imaging system and method for producing semiconductor structures on a wafer by imaging a mask on the wafer with a dipole diaphragm
    16.
    发明申请
    Imaging system and method for producing semiconductor structures on a wafer by imaging a mask on the wafer with a dipole diaphragm 审中-公开
    通过用偶极子膜片将晶片上的掩模成像在晶片上制造半导体结构的成像系统和方法

    公开(公告)号:US20060183258A1

    公开(公告)日:2006-08-17

    申请号:US11334941

    申请日:2006-01-19

    IPC分类号: G06F17/50 H01L21/00

    摘要: An imaging system having a dipole diaphragm (2) having two diaphragm openings (2b) arranged one behind the other in a dipole axis (y), and a mask having mask structures (20, 23) is used for producing semiconductor structures (10′, 13′) on a wafer (15′) by imaging the mask (25) onto the wafer (15′). The dipole diaphragm (2) is provided for the imaging of the mask (25), and the mask (25), for producing main semiconductor structures (10; 10′) on the wafer (15′), has main mask structures (20) parallel to an imaging axis (x) running perpendicular to the dipole axis (y). At least one connecting mask structure (23′) oriented obliquely with respect to the dipole axis (y) at least in sections is formed on the mask (25), which structure connects at least two main mask structures (20) to one another.

    摘要翻译: 一种具有偶极子(2)的成像系统,其具有在偶极轴(y)中一个彼此排列的两个隔膜开口(2b)和具有掩模结构(20,23)的掩模,用于制造半导体结构 ',13')通过将掩模(25)成像到晶片(15')上而在晶片(15')上。 提供偶极隔膜(2)用于掩模(25)的成像,并且用于在晶片(15')上制造主半导体结构(10; 10')的掩模(25)具有主掩模结构(20 )平行于垂直于偶极轴(y)延伸的成像轴(x)。 在掩模(25)上形成至少一部分相对于偶极轴(y)倾斜定向的至少一个连接掩模结构(23'),该结构将至少两个主掩模结构(20)彼此连接。

    Method for producing semiconductor patterns on a wafer
    17.
    发明申请
    Method for producing semiconductor patterns on a wafer 审中-公开
    在晶片上制造半导体图案的方法

    公开(公告)号:US20060177773A1

    公开(公告)日:2006-08-10

    申请号:US11335152

    申请日:2006-01-19

    IPC分类号: G03F7/00

    摘要: A method is used to produce semiconductor patterns (10′, 13′) on a wafer (15′). For this purpose, a mask (25) and a dipole aperture (2) with two aperture openings (2b) arranged behind one another in a dipole axis (y) are used. The mask (25) is imaged on the wafer (15′) by means of the dipole aperture (2) and, by the imaging of the mask (25) on the wafer (15′), main semiconductor patterns (10′) are produced which are aligned perpendicularly to the dipole axis (y) and in parallel with an imaging axis (x). A second mask (35) with at least one connecting mask pattern (33) is imaged on the wafer (15′) by means of a second aperture (6), as a result of which a connecting semiconductor pattern (13) is produced on the wafer (15′), by means of which at least two of the main semiconductor patterns (10′) are connected to one another.

    摘要翻译: 使用一种方法来在晶片(15')上产生半导体图案(10',13')。 为此,使用具有在偶极轴(y)中彼此相邻布置的两个开口开口(2b)的掩模(25)和偶极孔(2)。 通过偶极孔(2)将掩模(25)成像在晶片(15')上,并且通过在晶片(15')上的掩模(25)的成像,主半导体图案(10') 产生的垂直于偶极轴(y)并与成像轴(x)平行排列。 具有至少一个连接掩模图案(33)的第二掩模(35)通过第二孔(6)被成像在晶片(15')上,结果在其上产生连接半导体图案(13) 所述晶片(15')通过所述晶片(15')中的至少两个所述主半导体图案(10')彼此连接。