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公开(公告)号：US08319548B2
公开(公告)日：2012-11-27
申请号：US12622277
申请日：2009-11-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
发明人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
IPC分类号： G05F1/10
摘要： A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.
摘要翻译： 电压调节器调节节点处的电压，并且具有耦合到节点的电路以向节点提供电流。 耦合在节点和第一电源电压端子之间的调节晶体管具有并联耦合的禁用晶体管，并且通过将第一电源电压端子直接连接到节点来选择性地禁止。 反相级具有连接到调节晶体管的输出端。 负载晶体管具有耦合到第二电源电压端子的第一电流电极和连接在一起并耦合到反相级的输入端的控制电极和第二电流电极。 感测晶体管具有耦合到负载晶体管的第二电流电极的第一电流电极，直接连接到节点的控制电极和耦合到第一电源电压端子的第二电流电极。
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公开(公告)号：US20110116328A1
公开(公告)日：2011-05-19
申请号：US12620314
申请日：2009-11-17
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1075 , G11C7/18 , G11C19/00 , G11C19/28
摘要： An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.
摘要翻译： 存储器位单元阵列可操作以提供具有数据移位能力的存储器件，从而能够以并行和串行方式从存储器件灵活地存储和检索数据。 因此，存储器阵列可以用于常规存储器存储操作，并且还可以用于提供对存储的数据元素的布置的改变的诸如矩阵操作的操作。
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公开(公告)号：US20110066918A1
公开(公告)日：2011-03-17
申请号：US12560999
申请日：2009-09-16
CPC分类号： G06F11/1012
摘要： A memory system includes a memory array. The memory array includes a plurality of storage locations arranged in rows and columns. The memory system includes error correction circuitry that generates correct data bits from data bits of the memory array and error correction bits. The data bits received by the error correction circuitry are divided in subgroups where each subgroup of data bits is used to generate a subgroup of the correct data bits. The subgroups of data bits are stored in a row of the memory array at locations that are interleaved with each other.
摘要翻译： 存储器系统包括存储器阵列。 存储器阵列包括以行和列布置的多个存储位置。 存储器系统包括纠错电路，其从存储器阵列的数据位和纠错位产生正确的数据位。 由纠错电路接收的数据位被划分成子组，其中每个子组的数据位用于产生正确数据位的子组。 数据位的子组在相互交错的位置存储在存储器阵列的一行中。
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14.发明授权公开(公告)号：US07669034B2
公开(公告)日：2010-02-23
申请号：US11257932
申请日：2005-10-25
IPC分类号： G06F12/00
摘要： A method and data processing system for accessing an entry in a memory array is provided using base and offset addresses without adding the base and offset addresses. PGZO encoding is performed on the address bits of the operands. The PGZO values are evaluated using wordline generators resulting in a plurality of possible memory array entry addresses. In parallel with the PGZO operations, a carry value is generated using other bits in the operands. The result of the carry operation determines which of the possible memory array entries is selected from the memory array.
摘要翻译： 使用基地址和偏移地址提供访问存储器阵列中的条目的方法和数据处理系统，而不添加基址和偏移地址。 对操作数的地址位执行PGZO编码。 使用字线生成器来评估PGZO值，得到多个可能的存储器阵列入口地址。 与PGZO操作并行，使用操作数中的其他位生成进位值。 进位操作的结果确定从存储器阵列中选择哪个可能的存储器阵列条目。
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公开(公告)号：US09021194B2
公开(公告)日：2015-04-28
申请号：US13213900
申请日：2011-08-19
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译： 一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126） 不使用操作数加法器的输出和从操作数（111,113）中读出。 将来自操作数（111,113）的PGZ编码的地址位（0:51）与进位值（Cout48）一起施加到内容寻址存储器阵列（114），以产生两个推测的命中/未命中信号。 从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。
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公开(公告)号：US08710916B2
公开(公告)日：2014-04-29
申请号：US13020565
申请日：2011-02-03
CPC分类号： H03K19/0008 , H03K19/0016
摘要： An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.
摘要翻译： 电子电路包括多个电路块，多个偏置电路，开关电路和多个晶体管。 多个电路块各自包括高功率端子和低功率端子。 开关电路包括多个开关，用于将多个偏置电路的偏置电路选择性地耦合到多个电路块的电路块的低功率端子。 多个偏置电路的每个偏置电路可以选择性地耦合到多个电路块中的每一个的低功率端子。 多个晶体管的每个晶体管具有耦合到电路接地端子的第一电流端子，并且多个晶体管中的每个晶体管具有控制端子，用于通过多个偏置的偏置电路来控制多个晶体管的导电性 电路。
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17.发明申请TECHNIQUE FOR DETERMINING IF A LOGICAL SUM OF A FIRST OPERAND AND A SECOND OPERAND IS THE SAME AS A THIRD OPERAND 有权如果第一个操作的逻辑关系和第二个操作与第三个操作相同，则用于确定的技术公开(公告)号：US20100306302A1
公开(公告)日：2010-12-02
申请号：US12474451
申请日：2009-05-29
CPC分类号： G06F7/02 , G06F7/48 , G06F12/0864
摘要： A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.
摘要翻译： 系统用于确定第一操作数和第二操作数的和是否与第三操作数相同，其中与第三操作数的比较具有可变长度。 这在内容可寻址存储器（CAM）中特别有用，其中命中的可能性在集合的关联高速缓存中通常被改善，并允许CAM识别不同的事物。 例如，条目可以是识别存储器的页面的一个长度，而另一个条目是不同的长度以标识存储器页面。 通过参考以下描述和附图可以更好地理解这一点。
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18.发明申请公开(公告)号：US20080222361A1
公开(公告)日：2008-09-11
申请号：US11684529
申请日：2007-03-09
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , Y02D10/13
摘要： A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. In some cases, phased access can be described as pipelined tag and information array access, though strictly speaking, indexing into the information array need not depend on results of the tag array access. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.
摘要翻译： 描述了一种高速缓存设计，其中对标签和信息数组的相应访问在时间上是相位的，并且其中从标签数组中检索（通常是推测性地）的标签，而不受随后用于从信息数组的相应检索的有效地址计算的益处 。 在一些开发中，这样的设计可以允许存储器子系统的周期时间（和吞吐量）更接近地匹配一些处理器和计算系统架构的需求。 在某些情况下，分阶段访问可以被描述为流水线标签和信息数组访问，但严格来说，索引到信息数组不需要依赖于标签数组访问的结果。 我们的技术旨在允许从标签数组中提前（确实是推测性的）检索，而不会延迟，否则将与从信息数组中相应检索最终采用的有效地址的计算相关联。 可以使用最终计算的有效地址或使用单独的功能来解决投机。 在一些实施例中，我们使用基于从标签阵列检索的标签的方法选择的计算的有效地址。
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19.发明授权Integrated circuit storage element having low power data retention and method therefor 有权具有低功率数据保持的集成电路存储元件及其方法公开(公告)号：US07187205B2
公开(公告)日：2007-03-06
申请号：US11065793
申请日：2005-02-25
IPC分类号： H03K19/0175
CPC分类号： H03K3/356008
摘要： A storage element (10) includes a first latch (12) and a second latch (14). The first latch (12) is coupled to a first power supply voltage terminal for receiving a first power supply voltage. The second latch (14) is coupled to a second power supply voltage terminal. The second power supply voltage terminal for receiving a second power supply voltage that is lower than the first power supply voltage. During a normal mode of operation, the second power supply voltage is not provided to the second latch. During a low power mode of operation data is transferred from the first latch to the second latch and the first latch is powered down. The data is retained by the second latch while in low power mode.
摘要翻译： 存储元件（10）包括第一闩锁（12）和第二闩锁（14）。 第一锁存器（12）耦合到第一电源电压端子，用于接收第一电源电压。 第二锁存器（14）耦合到第二电源电压端子。 所述第二电源电压端子用于接收低于所述第一电源电压的第二电源电压。 在正常操作模式期间，第二电源电压不被提供给第二锁存器。 在低功率操作模式期间，数据从第一锁存器传送到第二锁存器，并且第一锁存器掉电。 在低功率模式下，数据由第二个锁存器保留。
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公开(公告)号：US07843218B1
公开(公告)日：2010-11-30
申请号：US12607657
申请日：2009-10-28
IPC分类号： H03K19/173
CPC分类号： G01R31/318541
摘要： A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latch (540) generates a flip flop output signal at a launch time under control of a slave clock signal, clock generation circuitry (550) generates a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode, and data propagation logic circuitry (564) uses the first and second clock signals to generate the master and slave clock signals during a scan mode to delay the launch time of the slave latch with respect to the hold time of the master latch.
摘要翻译： 描述了多路复用数据触发器电路（500），其中复用器（510）输出功能或扫描数据，主锁存器（520）在主时钟信号的控制下在保持时间产生主锁存器输出信号， 从锁存器（540）在从时钟信号的控制下在启动时产生触发器输出信号，时钟产生电路（550）产生在功能模式期间具有DC状态的第二时钟信号，并且在第一时钟信号期间具有开关状态 扫描模式和数据传播逻辑电路（564）在扫描模式期间使用第一和第二时钟信号来产生主时钟信号和从时钟信号，以相对于主锁存器的保持时间延迟从锁存器的启动时间。
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