公开(公告)号：US07289336B2

公开(公告)日：2007-10-30

申请号：US10975952

申请日：2004-10-28

申请人： William Edward Burdick, Jr. ,  James Wilson Rose ,  John Eric Tkaczyk ,  Oded Meirav ,  Jerome Stephen Arenson ,  David Michael Hoffman

发明人： William Edward Burdick, Jr. ,  James Wilson Rose ,  John Eric Tkaczyk ,  Oded Meirav ,  Jerome Stephen Arenson ,  David Michael Hoffman

IPC分类号： H05K1/11

CPC分类号： H05K1/147 ,  H05K2201/10151

摘要： An interconnect structure for use in an electronic device, wherein the interconnect structure comprises a first substrate comprising a flexible material, wherein the first substrate comprises a front side and a back side, and wherein the first substrate is configured to receive a sensor on the front side; and a second substrate coupled to the back side of the first substrate and comprising a rigid material. A detector module for use in an imaging system comprises the aforementioned interconnect structure.

摘要翻译： 一种用于电子设备的互连结构，其中所述互连结构包括包括柔性材料的第一基底，其中所述第一基底包括前侧和后侧，并且其中所述第一基底构造成在前面接收传感器 侧; 以及耦合到所述第一基板的背面并且包括刚性材料的第二基板。 用于成像系统的检测器模块包括上述互连结构。

公开(公告)号：US06239482B1

公开(公告)日：2001-05-29

申请号：US09334572

申请日：1999-06-21

申请人： Raymond Albert Fillion ,  William Edward Burdick, Jr. ,  Ronald Frank Kolc ,  James Wilson Rose ,  Glenn Scott Claydon

发明人： Raymond Albert Fillion ,  William Edward Burdick, Jr. ,  Ronald Frank Kolc ,  James Wilson Rose ,  Glenn Scott Claydon

IPC分类号： H01L2302

CPC分类号： H01L24/25 ,  H01L23/13 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

摘要： An integrated circuit package includes at least one integrated circuit element coupled to a polymer film; a window frame coupled to the polymer film and surrounding the at least one integrated circuit element; and encapsulant material positioned between the at least one integrated circuit element and the window frame.

摘要翻译： 集成电路封装包括耦合到聚合物膜的至少一个集成电路元件; 耦合到所述聚合物膜并围绕所述至少一个集成电路元件的窗框; 以及位于所述至少一个集成电路元件和所述窗框之间的密封材料。

公开(公告)号：US6150719A

公开(公告)日：2000-11-21

申请号：US900141

申请日：1997-07-28

申请人： Richard Joseph Saia ,  Kevin Matthew Durocher ,  James Wilson Rose

发明人： Richard Joseph Saia ,  Kevin Matthew Durocher ,  James Wilson Rose

IPC分类号： B32B7/02 ,  B32B9/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49894 ,  H01L24/18 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14

摘要： A hard layer of amorphous hydrogenated carbon (DLC) overlies a polymer film structure and a plurality of soft layers of DLC alternate with a plurality of hard layers of DLC over the barrier base to form a corrosion resistant structure. The polymer film structure and a circuit chip can be elements of a circuit module. The DLC and the polymer film structure can have vias extending to contact pads, and a pattern of electrical conductors can extend through the vias to the contact pads. In one embodiment the DLC forms a hermetic (and therefore corrosion resistant) seal over the polymer film structure.

摘要翻译： 无定形氢化碳（DLC）的硬层覆盖聚合物膜结构，并且DLC的多个软层与阻挡层上的多个DLC硬层交替形成耐腐蚀结构。 聚合物膜结构和电路芯片可以是电路模块的元件。 DLC和聚合物膜结构可以具有延伸到接触焊盘的通孔，并且电导体的图案可以延伸穿过通孔到接触焊盘。 在一个实施方案中，DLC在聚合物膜结构上形成密封（因此是耐腐蚀的）密封。

公开(公告)号：US6040226A

公开(公告)日：2000-03-21

申请号：US177908

申请日：1998-10-23

申请人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

发明人： Robert John Wojnarowski ,  James Wilson Rose ,  Ernest Wayne Balch ,  Leonard Richard Douglas ,  Evan Taylor Downey ,  Michael Gdula

IPC分类号： H01L21/20

CPC分类号： H01L21/20

摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.

摘要翻译： 提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。 电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。 薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。 可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。

公开(公告)号：US20130319759A1

公开(公告)日：2013-12-05

申请号：US13485526

申请日：2012-05-31

申请人： James Wilson Rose ,  Kaustubh Ravindra Nagarkar ,  Craig Patrick Galligan ,  Binoy Milan Shah ,  Oliver Richard Astley

发明人： James Wilson Rose ,  Kaustubh Ravindra Nagarkar ,  Craig Patrick Galligan ,  Binoy Milan Shah ,  Oliver Richard Astley

IPC分类号： H02G15/02 ,  H01B13/00

CPC分类号： H01L24/43 ,  H01L24/46 ,  H01L2224/43 ,  H01L2224/45014 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H05K1/118 ,  H05K2203/0235 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/206

摘要： A flexible wire assembly includes a plurality of elongated conductors and insulators each having a quadrilateral cross section and alternatingly laminated together, the flexible wire assembly having a wire width measured across the conductor and insulators, a wire height equivalent to the height of the conductors and insulators, and a wire length which is measured in a longitudinal direction orthogonal to the wire width and the wire height, wherein the wire length is one or more orders of magnitude greater than the wire width and the wire height; and a first device comprising a plurality of bond pads spaced to define a bond pad pitch, wherein the flexible wire assembly is coupled to the first device at the bond pads such that spacing of the conductor conductors is matched to the bond pad pitch.

摘要翻译： 柔性线组件包括多个细长导体和绝缘体，每个细长导体和绝缘体具有四边形横截面并交替层压在一起，柔性线组件具有跨导体和绝缘体测量的导线宽度，线高度等于导体和绝缘体的高度 以及在与线宽度和线高度正交的纵向方向上测量的线长度，其中线长度比线宽和线高度大一个或多个数量级; 以及包括间隔开以限定接合焊盘间距的多个接合焊盘的第一器件，其中所述柔性线组件在所述接合焊盘处耦合到所述第一器件，使得所述导体导体的间隔与所述接合焊盘间距匹配。

公开(公告)号：US07606347B2

公开(公告)日：2009-10-20

申请号：US11744292

申请日：2007-05-04

申请人： John Eric Tkaczyk ,  Jonathan D. Short ,  James Wilson Rose ,  Xiaoye Wu ,  Samit Kumar Basu

发明人： John Eric Tkaczyk ,  Jonathan D. Short ,  James Wilson Rose ,  Xiaoye Wu ,  Samit Kumar Basu

IPC分类号： A61B6/03

CPC分类号： A61B6/5205 ,  A61B6/032 ,  A61B6/4291 ,  G01T1/2018 ,  G01T1/242 ,  G01T1/243 ,  G01T1/249

摘要： A CT detector includes a first detector configured to convert radiographic energy to electrical signals representative of energy sensitive radiographic data and a second detector configured to convert radiographic energy to electrical signals representative of energy sensitive radiographic data and positioned to receive x-rays that pass through the first detector. A logic controller is electrically connected to the first detector and the second detector and is configured to receive a logic output signal from the second detector indicative of an amount of a saturation level of the first detector, compare the logic output signal to a threshold value, and output, based on the comparison, electrical signals from the first detector, the second detector, or a combination thereof to an image chain.

摘要翻译： CT检测器包括：第一检测器，其被配置为将射线照相能量转换成表示能量敏感射线照相数据的电信号;以及第二检测器，被配置为将放射线照相能量转换成表示能量敏感射线照相数据的电信号，并被定位成接收穿过 第一检测器 逻辑控制器电连接到第一检测器和第二检测器，并且被配置为从第二检测器接收指示第一检测器的饱和电平的量的逻辑输出信号，将逻辑输出信号与阈值进行比较， 并且基于比较将来自第一检测器，第二检测器或其组合的电信号输出到图像链。

公开(公告)号：US20080213933A1

公开(公告)日：2008-09-04

申请号：US12117608

申请日：2008-05-08

申请人： RAYETTE ANN FISHER ,  William Edward Burdick ,  James Wilson Rose

发明人： RAYETTE ANN FISHER ,  William Edward Burdick ,  James Wilson Rose

IPC分类号： H01L21/50

CPC分类号： H01L27/14601

摘要： Methods of fabricating a tiled transducer array are disclosed. Embodiments of the methods include fabricating a wafer comprising a plurality of transducers, dicing the wafer to form individual transducers, testing the individual transducers to identify a plurality of known good transducers, preparing a substrate having a front side and a backside wherein the backside of the substrate comprises a plurality of connectors, positioning the plurality of known good transducers on the front side of the substrate and aligning the plurality of transducers in a horizontal direction and a vertical direction to form a transducer array, and electrically coupling the connectors on the substrate to the plurality of known good transducers, wherein the connectors are arranged such that each of the plurality of known good transducers may be electrically coupled to an electronic device disposed on the backside of the substrate, through a respective one or more of the plurality of connectors.

摘要翻译： 公开了制作平铺式换能器阵列的方法。 所述方法的实施例包括制造包括多个换能器的晶片，切割晶片以形成单独的换能器，测试各个换能器以识别多个已知的良好换能器，制备具有正面和背面的基底，其中背面 衬底包括多个连接器，将多个已知的良好换能器定位在衬底的前侧上并且在水平方向和垂直方向上对准多个换能器以形成换能器阵列，并将衬底上的连接器电耦合到 所述多个已知的良好换能器，其中所述连接器被布置成使得所述多个已知的良好换能器中的每一个可以通过所述多个连接器中的相应一个或多个电耦合到设置在所述基板的背面上的电子装置。

公开(公告)号：US07112877B2

公开(公告)日：2006-09-26

申请号：US10877256

申请日：2004-06-28

申请人： William Edward Burdick, Jr. ,  James Wilson Rose ,  Michael Anthony Rumsey

发明人： William Edward Burdick, Jr. ,  James Wilson Rose ,  Michael Anthony Rumsey

IPC分类号： H01L23/48

CPC分类号： H01R12/62 ,  H01L23/4985 ,  H01L23/5387 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/118 ,  H05K1/189 ,  H05K2201/056 ,  H05K2201/10719 ,  H01L2924/00

摘要： A high density electrical interconnecting system of the present invention has at least one substrate piece and a flexible wrap-around interconnect assembly extending from a first surface of the substrate piece to a second surface of the substrate piece wherein the flexible wrap-around interconnect is disposed around an outer surface of the substrate piece.

摘要翻译： 本发明的高密度电互连系统具有至少一个基片和柔性环绕互连组件，该基片和柔性环绕互连组件从基片的第一表面延伸到基片的第二表面，其中布置柔性环绕互连 围绕基片的外表面。

公开(公告)号：US06737002B1

公开(公告)日：2004-05-18

申请号：US10067077

申请日：2002-02-04

申请人： James Wilson Rose ,  Donald Leroy Lester ,  Christopher James Kapusta ,  Paul Alan McConnelee

发明人： James Wilson Rose ,  Donald Leroy Lester ,  Christopher James Kapusta ,  Paul Alan McConnelee

IPC分类号： B29C4514

CPC分类号： B29C70/70

摘要： A chip-on-flex HDI module is fabricated by dispensing encapsulant material onto the components of a populated dielectric film or sheet in an interrupted pattern which leaves the backsides of selected components free of encapsulant. The dispensing is accomplished by relative motion of the dispenser tip and the populated film, with the dispenser tip at a height slightly above the desired liquid fill height during dispensing. At the locations of the components which are to be free of encapsulant, the dispensing stops, and the tip may be raised to prevent residual viscous matter on the dispenser tip from contacting the backside of the exposed component.

摘要翻译： 通过将密封剂材料以间断的图案分配填充的电介质膜或片材的组件来制造柔性片上HDI模块，这使得所选部件的背面不含密封剂。 分配是通过分配器尖端和填充膜的相对运动来实现的，其中分配器尖端在分配期间略高于期望的液体填充高度的高度。 在不含密封剂的部件的位置处，分配停止，并且尖端可以升高以防止分配器尖端上的残留粘性物质接触暴露部件的背面。

公开(公告)号：US06602739B1

公开(公告)日：2003-08-05

申请号：US10101231

申请日：2002-03-19

申请人： James Wilson Rose ,  Thomas Bert Gorczyca ,  Christopher James Kapusta ,  Ernest Wayne Balch ,  Kevin Matthew Durocher

发明人： James Wilson Rose ,  Thomas Bert Gorczyca ,  Christopher James Kapusta ,  Ernest Wayne Balch ,  Kevin Matthew Durocher

IPC分类号： H01L2144

CPC分类号： H01L24/76 ,  H01L21/4857 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2224/81801 ,  H01L2224/82039 ,  H01L2224/92144 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K1/185

摘要： A method for making a multichip “HDI” module includes the step of making a substrate for supporting the semiconductor or solid-state chips (or other components) by applying electrical conductor in a pattern to a first dielectric sheet, and applying encapsulating material to the electrical conductor. Apertures are made in the first dielectric sheet and encapsulant at locations at which the chips (or other components) are to be located. The components are affixed to a second dielectric sheet at locations registered with the apertures in the first sheet, and the sheets are juxtaposed with the chips extending into the apertures. This results in the formation of gaps between the components and the edges of the apertures, which gaps are then filled with hardenable or curable material. Electrical connection is made to the pads of the chips by means of a multilayer structure of dielectric sheets with conductor patterns, interconnected by means of plated-through vias.

摘要翻译： 制造多芯片“HDI”模块的方法包括以下步骤：通过将图案中的电导体施加到第一电介质片上，并且将封装材料施加到第一电介质片上，制备用于支撑半导体或固态芯片（或其它部件）的基板 电导体。 在第一电介质片和密封剂中在芯片（或其他部件）所在的位置处形成孔。 这些部件在与第一片中的孔对准的位置处固定到第二电介质片，并且片材与延伸到孔中的芯片并置。 这导致在部件和孔的边缘之间形成间隙，然后用可硬化或可固化材料填充该间隙。 通过具有通过电镀通孔互连的导体图案的介电片的多层结构对芯片的焊盘进行电连接。