公开(公告)号：US5495611A

公开(公告)日：1996-02-27

申请号：US902311

申请日：1992-06-22

申请人： Richard Bealkowski ,  John W. Blackledge, Jr. ,  Douglas R. Geisler ,  Michael R. Turner

发明人： Richard Bealkowski ,  John W. Blackledge, Jr. ,  Douglas R. Geisler ,  Michael R. Turner

IPC分类号： G06F9/445 ,  G06F9/00

CPC分类号： G06F9/4403

摘要： A personal computer system is disclosed which is compatible with application programs and operating system software. The personal computer system includes a microprocessor electrically coupled to a data bus, non-volatile memory electrically coupled to the data bus, volatile memory electrically responsive to the data bus, a memory controller electrically coupled to the microprocessor, the volatile memory and the non-volatile memory, and a direct access storage device electrically responsive to the data bus. The non-volatile memory stores a first portion of operating system microcode and the volatile memory includes a volatile operating system portion intended for use by the first portion of the operating system microcode. The memory controller regulates communications between the volatile memory, the non-volatile memory and the high speed microprocessor. The direct access storage device stores a second portion of operating system microcode which is accessed by the microprocessor as needed.

摘要翻译： 公开了一种与应用程序和操作系统软件兼容的个人计算机系统。 个人计算机系统包括电耦合到数据总线的微处理器，电耦合到数据总线的非易失性存储器，电响应于数据总线的易失性存储器，电耦合到微处理器的存储器控​​制器，易失性存储器和非易失性存储器， 易失性存储器，以及对数据总线电气响应的直接存取存储装置。 非易失性存储器存储操作系统微代码的第一部分，并且易失性存储器包括旨在由操作系统微代码的第一部分使用的易失性操作系统部分。 存储器控制器调节易失性存储器，非易失性存储器和高速微处理器之间的通信。 直接存取存储装置存储由微处理器根据需要访问的操作系统微代码的第二部分。

公开(公告)号：US5533205A

公开(公告)日：1996-07-02

申请号：US220326

申请日：1994-03-30

申请人： John W. Blackledge, Jr. ,  Bradly G. Frey

发明人： John W. Blackledge, Jr. ,  Bradly G. Frey

IPC分类号： G06F15/16 ,  G06F9/52 ,  G06F13/362 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F13/3625

摘要： A method and system for efficient bus allocation in a multimedia computer system which includes a processor, a memory and multiple input/output devices which are coupled together via a bus which has a maximum data transfer rate. The transfer of audio, video, or other time sensitive data within the computer system to various presentation devices must be accomplished at certain predetermined rates in order to support selected applications. An arbitration level indicator which may be utilized to indicate a priority of bus access is associated with each presentation device which may contend for bus access. The bus access is then divided into a series of time frames which are subdivided into smaller time intervals. During selected time intervals the arbitration level indicators associated with a particular presentation devices are temporarily reordered to guarantee bus access at the required data rate.

摘要翻译： 一种用于多媒体计算机系统中有效总线分配的方法和系统，其包括处理器，存储器以及通过具有最大数据传输速率的总线耦合在一起的多个输入/输出设备。 音频，视频或计算机系统内的其他时间敏感数据传输到各种显示设备必须以某些预定速率完成，以便支持所选择的应用。 可以用于指示总线访问的优先级的仲裁级指示符与可能争取总线访问的每个呈现设备相关联。 然后，总线访问被分成一系列时间间隔，其被细分为较小的时间间隔。 在选定的时间间隔期间，与特定表现设备相关联的仲裁级别指示器被暂时重新排序，以保证所需数据速率下的总线访问。