公开(公告)号：US20230376733A1

公开(公告)日：2023-11-23

申请号：US18198579

申请日：2023-05-17

申请人： RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY

发明人： Santosh Nagarakatte ,  Richard P. Martin ,  Mohammadreza Soltaniyeh

IPC分类号： G06N3/0464 ,  G06F17/16

CPC分类号： G06N3/0464 ,  G06F17/16

摘要： A hardware accelerator for neural network applications can include an image-to-column block and a general matrix-matrix multiplication (GEMM) block. The image-to-column block includes an input controller coupled to receive an input feature map from a memory block; a series of patch units configured in a ring network and coupled to the input controller to receive new elements of the input feature map; and an output controller coupled to receive each output patch from the series of patch units. The GEMM block can be a dynamically reconfigurable unit that can be configured as a tall array or individual square arrays. The described hardware accelerator can handle sparsity in both the feature map inputs (output from the image-to-column block) and the filter/weight inputs to the GEMM block.