公开(公告)号：US10033352B2

公开(公告)日：2018-07-24

申请号：US15053176

申请日：2016-02-25

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Germano Nicollini ,  Roberto Modaffari ,  Marco Garbarino ,  Federico Guanziroli

IPC: G01C17/38 ,  H03H11/18 ,  G01C19/5776 ,  G01C25/00

Abstract: A phase shifter, which carries out a ninety-degree phase shift of a sinusoidal input signal having an input frequency, at the same input frequency, envisages: a continuous-time all-pass filter stage, which receives the sinusoidal input signal and generates an output signal phase-shifted by 90° at a phase-shift frequency that is a function of a RC time constant of the all-pass filter stage; and a calibration stage, which is coupled to the all-pass filter stage and generates a calibration signal for the all-pass filter stage, such that the phase-shift frequency is equal to the input frequency of the sinusoidal input signal, irrespective of variations of the value of the input frequency and/or of the RC time constant with respect to a nominal value.

公开(公告)号：US20180026618A1

公开(公告)日：2018-01-25

申请号：US15394472

申请日：2016-12-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Germano Nicollini ,  Roberto Modaffari

IPC: H03K5/24

CPC classification number: H03K5/2481 ,  G01R19/0038 ,  H03F3/45179 ,  H03F3/45273 ,  H03K3/0377 ,  H03K5/24

Abstract: A comparator circuit including: a first node and a second node, which receive a first current and a second current, respectively; a first current mirror, which includes a first load transistor and a first output transistor; and a second current mirror, which includes a second load transistor and a second output transistor. The comparator circuit further includes: a first feedback transistor and a second feedback transistor cross-coupled together, the control terminals of the first and second feedback transistors being connected to the first and second nodes, respectively; a first resistor, having a first terminal, which is connected to the control terminal of the first load transistor, and a second terminal, which is connected to the first node and to the control terminal of the first output transistor; and a second resistor, having a first terminal, connected to the control terminal of the second load transistor, and a second terminal, connected to the second node and to the control terminal of the second output transistor.