公开(公告)号：US20200381617A1

公开(公告)日：2020-12-03

申请号：US16879577

申请日：2020-05-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Daniel BENOIT ,  Remy BERTHELON

IPC: H01L45/00 ,  H01L27/24

Abstract: The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities; and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.

公开(公告)号：US20190363190A1

公开(公告)日：2019-11-28

申请号：US16534557

申请日：2019-08-07

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy BERTHELON ,  Francois ANDRIEU

IPC: H01L29/78 ,  H01L21/762 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L21/84 ,  H01L27/12

Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.

公开(公告)号：US20190027560A1

公开(公告)日：2019-01-24

申请号：US16039771

申请日：2018-07-19

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

Inventor： François ANDRIEU ,  Remy BERTHELON

IPC: H01L29/10 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/74 ,  H01L21/266

Abstract: An integrated circuit includes a substrate; a buried insulating layer; at least one nMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one pMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one semiconductor groundplane that may be doped or a metal, placed above the substrate and below the buried insulating layer, said buried plane being common to the nMOS transistor and to the pMOS transistor; at least one gate insulator and a gate that is common to the nMOS transistor and to the pMOS transistor and that is located above the channel of these transistors and facing the groundplane, the area of the groundplane at least covering the area of the gate in vertical projection; the nMOS transistor being separated from the pMOS transistor by an isolation defined between the semiconductor layer of the nMOS transistor and the semiconductor layer of the pMOS transistor, the isolation being located in the buried insulating layer and making contact with the groundplane; at least one shared contact making electrical contact with the common gate and with the common groundplane, the shared contact passing through the buried insulating layer or the isolation.