公开(公告)号：US20150043681A1

公开(公告)日：2015-02-12

申请号：US13960213

申请日：2013-08-06

Applicant: STMicroelectronics International N.V.

Inventor： Sajal Kumar Mandal

IPC: H04L1/00 ,  G11C27/02

CPC classification number: G11C27/026

Abstract: A circuit includes: a first circuit stage configured to sample a differential input signal at a first logic state of a sampling clock and regenerate the sampled differential input signal at a second logic state of the sampling clock to output a first regenerated differential signal; a second circuit stage configured to amplify the first regenerated differential signal at the second logic state of the sampling clock to output an amplified differential signal; and a third circuit stage configured to regenerate the amplified differential signal at the first logic state of the sampling clock to output a second regenerated differential signal.

Abstract translation: 电路包括：第一电路级，被配置为在采样时钟的第一逻辑状态下对差分输入信号进行采样，并在采样时钟的第二逻辑状态下重新产生采样的差分输入信号，以输出第一再生的差分信号; 第二电路级，被配置为在采样时钟的第二逻辑状态下放大第一再生差分信号，以输出放大的差分信号; 以及第三电路级，被配置为在采样时钟的第一逻辑状态下再生放大的差分信号，以输出第二再生的差分信号。