公开(公告)号：US20240431140A1

公开(公告)日：2024-12-26

申请号：US18420144

申请日：2024-01-23

Applicant: Samsung Display Co., LTD.

Inventor： Chul SHIN ,  Jin Mo KWON ,  Won Jin SEO ,  Hwa An SUNG ,  Ji Young EOM ,  Dae Ho HWANG

IPC: H10K59/121 ,  H10K59/35 ,  H10K102/10

Abstract: A display device according to an embodiment includes a display area including a first display area and a second display area disposed around the first display area, a first pixel disposed in the first display area and including a first emission area, and a second pixel disposed in the second display area and including a second emission area, wherein the second emission area has a larger size than the first emission area.

公开(公告)号：US20220084469A1

公开(公告)日：2022-03-17

申请号：US17318289

申请日：2021-05-12

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Ki Hyun PYUN ,  Jang Hoon KWAK ,  Won Jin SEO

IPC: G09G3/3266

Abstract: A display device includes a display panel including scan lines, first signal lines connected to the scan lines in a first pixel block, second signal lines connected to the scan lines in a second pixel block, third signal lines connected to the scan lines in a third pixel block; a first scan driver supplying a first output signal to the first signal lines based on a first sub-clock signal; a second scan driver supplying a second output signal to the second signal lines based on a second sub-clock signal; a third scan driver supplying a third output signal to the third signal lines based on and a third sub-clock signal; and a timing controller. Changes in pulse widths of the first to third output signals are different in one frame period.

公开(公告)号：US20210281263A1

公开(公告)日：2021-09-09

申请号：US17087476

申请日：2020-11-02

Applicant: Samsung Display Co., Ltd.

Inventor： Ki Hyun PYUN ,  Won Jin SEO ,  Eun Jin CHOI

IPC: H03K19/0175 ,  H04B1/04 ,  G09G3/3233

Abstract: An interface system including: a receiver; a transmitter configured to transmit a signal including a common mode voltage to the receiver through transmission lines; and a plurality of bias circuits configured to adjust the common mode voltage of the signal, wherein the bias circuits are configured to receive a bias control bit to generate a biased common mode voltage.