公开(公告)号：US10998036B2

公开(公告)日：2021-05-04

申请号：US16678692

申请日：2019-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihwan Seong ,  Soomin Lee ,  Sanghune Park

IPC: G11C29/00 ,  G11C11/4076 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  H01L25/065

Abstract: A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.