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公开(公告)号：US11521977B2
公开(公告)日：2022-12-06
申请号：US17471824
申请日：2021-09-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kiseok Lee , Chan-Sic Yoon , Augustin Hong , Keunnam Kim , Dongoh Kim , Bong-Soo Kim , Jemin Park , Hoin Lee , Sungho Jang , Kiwook Jung , Yoosang Hwang
IPC: H01L27/108 , H01L27/24 , H01L27/22
Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.
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公开(公告)号：US20220139921A1
公开(公告)日：2022-05-05
申请号：US17372634
申请日：2021-07-12
Applicant: Samsung Electronics Co., Ltd
Inventor： EUNA KIM , Keunnam Kim , Kiseok Lee , Wooyoung Choi , Sunghee Han
IPC: H01L27/108 , H01L23/528
Abstract: A semiconductor device includes a substrate including an active region, a first bitline structure and a second bitline structure that extend side by side on the substrate, a storage node contact electrically connected to the active region between the first and second bitline structures, a lower landing pad between the first and second bitline structures and on the storage node contact, an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad, and a capping insulating layer. A lower surface of the upper landing pad in contact with the first bitline structure and a lower surface of the capping insulating layer in contact with the lower landing pad each include a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in a direction toward the substrate.
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公开(公告)号：US11126300B2
公开(公告)日：2021-09-21
申请号：US15598576
申请日：2017-05-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiseok Lee , Kyungwhoon Cheun , Dohy Hong , Sungkee Kim , Sungil Park , Changmin Ha
IPC: G06F3/041 , G06F3/0484 , G06F3/0488
Abstract: A method of processing an input in an electronic device having a touch screen is provided. The method includes identifying attribute information of a geometric figure corresponding to an area of a touch input detected through the touch screen, determining a user input from the attribute information, based on a stored user input distinction rule, and executing a function corresponding to the determined user input.
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公开(公告)号：US10685963B2
公开(公告)日：2020-06-16
申请号：US16242127
申请日：2019-01-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiseok Lee , Keunnam Kim , Eun A Kim , Eunjung Kim , Jeongseop Shim
IPC: H01L21/28 , H01L21/306 , H01L21/308 , H01L27/108 , H01L27/22 , H01L27/24 , H01L29/423
Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises forming an active structure including a plurality of active patterns, a device isolation layer defining the active patterns, and a gate structure across the active patterns and extending in a first direction, forming a first mask pattern on the active structure, and forming a trench by using the first mask pattern as an etching mask to pattern the active structure. Forming the first mask pattern comprises forming in a first mask layer a plurality of first openings extending in a second direction intersecting the first direction, and forming in the first mask layer a plurality of second openings extending in a third direction intersecting the first and second directions.
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公开(公告)号：US10524102B2
公开(公告)日：2019-12-31
申请号：US15165412
申请日：2016-05-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Jung Kim , Kiseok Lee
Abstract: The present disclosure relates to a sensor network, Machine Type Communication (MTC), Machine-to-Machine (M2M) communication, and technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The present disclosure provides a method for operating an electronic device. The method comprises transmitting a signal including a list of one or more objects, receiving a signal including beacon recognition information of at least one object included in the list of one or more objects, storing the beacon recognition information, and making a request for information on the at least one object to a server when receiving at least one beacon signal that matches with the stored beacon recognition information.
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公开(公告)号：US10026694B2
公开(公告)日：2018-07-17
申请号：US15608747
申请日：2017-05-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kiseok Lee , Sooho Shin , Juik Lee , Jun Ho Lee , Kwangmin Kim , Ilyoung Moon , Jemin Park , Bumseok Seo , Chan-Sic Yoon , Hoin Lee
IPC: H01L23/544 , H01L27/108
Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.
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公开(公告)号：US20240389308A1
公开(公告)日：2024-11-21
申请号：US18589891
申请日：2024-02-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongjun Lee , Seokhan Park , Iljae Shin , Kiseok Lee , Sanghyun Lee
IPC: H10B12/00 , H01L23/528 , H01L29/08 , H01L29/417
Abstract: A semiconductor device includes a substrate including a memory cell array region, a contact region, and a connection region, gate electrodes on the memory cell array region and the connection region, and stacked in a vertical direction, active layers on the memory cell array region and stacked in the vertical direction, and conductive connection patterns on the connection region and the contact region, and stacked in the vertical direction, wherein each of the active layers includes a channel region vertically overlapping the gate electrodes, the gate electrodes are electrically connected to the conductive connection patterns, the conductive connection patterns have a step structure including step regions spaced apart from each other, and the step structure has a first step portion stepping down along a first direction and a second step portion facing the first step portion and stepping up along the first direction.
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公开(公告)号：US20240357832A1
公开(公告)日：2024-10-24
申请号：US18512331
申请日：2023-11-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kiseok Lee , Jinwoo Han , Hanjin Lim
Abstract: A semiconductor device includes a bit line structures on a substrate, extending in a first direction, and being spaced apart from each other in a second direction; channels contacting upper surfaces of the bit line structures and being spaced apart from each other in the first and second directions; upper gate structures extending in the second direction and surrounding the channels disposed in the second direction, the upper gate structures being spaced apart in the first direction; and a capacitor structure including first capacitor electrodes respectively on the channels; a dielectric layer on the first capacitor electrodes, the dielectric layer including a ferroelectric material or an anti-ferroelectric material; a second capacitor electrode layer on the dielectric layer; and capacitor plate electrodes on the second capacitor electrode layer, the capacitor plate electrodes each extending in the second direction and being spaced apart from each other in the first direction.
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公开(公告)号：US20240224507A1
公开(公告)日：2024-07-04
申请号：US18541625
申请日：2023-12-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jongmin Kim , Taejin Park , Chansic Yoon , Kiseok Lee , Hongjun Lee
IPC: H10B12/00 , H01L29/417 , H01L29/423
CPC classification number: H10B12/34 , H01L29/41741 , H01L29/4236 , H10B12/315
Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure, a conductive filling pattern and a bit line structure on the conductive filling pattern. The gate structure extends through an upper portion of the active pattern, and has an upper surface higher than an upper surface of the active pattern. The conductive filling pattern includes a lower portion on the active pattern and an upper portion thereon. The lower portion contacts an upper sidewall of the gate structure, and the upper portion has a width greater than a width of the lower portion.
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20.发明公开
公开(公告)号：US20240170574A1
公开(公告)日：2024-05-23
申请号：US18518264
申请日：2023-11-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Joongchan Shin , Kiseok Lee , Seokhan Park , Seokho Shin
CPC classification number: H01L29/7827 , H10B12/0335 , H10B12/482 , H10B12/50
Abstract: A semiconductor device includes a vertical channel transistor including a vertical channel region extending in a vertical direction and a cell gate electrode facing a first side surface of the vertical channel region. A bit line is electrically connected to the vertical channel transistor at a level that is lower than a level of the vertical channel transistor. A peripheral semiconductor body has at least a portion thereof disposed on a same level as the vertical channel region. Peripheral source/drain regions are disposed in the peripheral semiconductor body and are spaced apart from each other in a horizontal direction. A peripheral channel region is disposed between the peripheral source/drain regions in the peripheral semiconductor body. A peripheral gate is disposed below the peripheral semiconductor body. At least a portion of the peripheral gate is disposed on a same level as at least a portion of the bit line.
