公开(公告)号：US20220208784A1

公开(公告)日：2022-06-30

申请号：US17695186

申请日：2022-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa YUN ,  Pansuk KWAK ,  Chanho KIM ,  Dongku KANG

IPC: H01L27/11573 ,  H01L27/1157 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US20220157754A1

公开(公告)日：2022-05-19

申请号：US17381782

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong PARK ,  Chanho KIM ,  Pansuk KWAK ,  Daeseok BYEON

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/66 ,  H01L25/00

Abstract: A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.

公开(公告)号：US20210043641A1

公开(公告)日：2021-02-11

申请号：US17001035

申请日：2020-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa YUN ,  Pansuk KWAK ,  Chanho KIM ,  Dongku KANG

IPC: H01L27/11573 ,  H01L27/1157 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.