公开(公告)号：US20220012127A1

公开(公告)日：2022-01-13

申请号：US17487506

申请日：2021-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WONHYUNG SONG ,  Taekwoon Kim ,  Hosung Yoon ,  Yoojung Lee ,  Jangseok Choi

IPC: G06F11/10 ,  G06F1/08 ,  G06F11/16 ,  G06F11/07

Abstract: A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.

公开(公告)号：US11157358B2

公开(公告)日：2021-10-26

申请号：US16861312

申请日：2020-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyung Song ,  Taekwoon Kim ,  Hosung Yoon ,  Yoojung Lee ,  Jangseok Choi

IPC: G06F11/10 ,  G06F11/16 ,  G06F11/07 ,  G06F1/08

Abstract: A memory module includes first memory chips, each having a first input/output width, and configured to store data, a second memory chip having a second input/output width and configured to store an error correction code for correcting an error in the data, and a driver circuit configured to receive a clock signal, a command, and an address from a memory controller and to transmit the clock signal, the command, and the address to the first memory chips and the second memory chip. An address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.