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    Semiconductor memory device and method of controlling the same
    11.
    发明授权
    Semiconductor memory device and method of controlling the same 有权
    半导体存储器件及其控制方法

    公开(公告)号：US08649238B2

    公开(公告)日：2014-02-11

    申请号：US13078218

    申请日：2011-04-01

    申请人： Dong-Min Kim ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    发明人： Dong-Min Kim ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    IPC分类号： G11C8/00

    CPC分类号： G11C8/12 ,  G11C8/18

    摘要： A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic circuit controls the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually operate in a second operation mode.

    摘要翻译： 半导体存储器件包括存储单元阵列，地址控制单元和逻辑电路。 存储单元阵列包括被划分成第一存储块和第二存储块的多个存储体。 地址控制单元访问存储单元阵列。 逻辑电路基于命令和地址信号控制地址控制单元，使得第一和第二存储体块以第一操作模式共同操作，并且第一和第二存储体块以第二操作模式分别操作。

    Receiving apparatus and method thereof
    13.
    发明授权
    Receiving apparatus and method thereof 有权
    接收装置及其方法

    公开(公告)号：US07822111B2

    公开(公告)日：2010-10-26

    申请号：US11345451

    申请日：2006-02-02

    申请人： Young-Soo Sohn ,  Seung-Jun Bae ,  Hong-Jun Park ,  Jung-Hwan Choi

    发明人： Young-Soo Sohn ,  Seung-Jun Bae ,  Hong-Jun Park ,  Jung-Hwan Choi

    IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

    CPC分类号： H04L25/03038 ,  H04L7/0058

    摘要： Example embodiments relate to a receiving apparatus and method thereof. In an example, the receiving apparatus may include a clock generating unit generating a plurality of internal clock signals based on a received external clock signal and an equalization receiving unit receiving the plurality of internal clock signals and an input signal. The equalization receiving unit may determine an offset value and an equalization coefficient in an initial setting mode and may adjust the received data signal based on the determined offset value and equalization coefficient.

    摘要翻译： 示例性实施例涉及一种接收设备及其方法。 在一个示例中，接收装置可以包括基于接收的外部时钟信号产生多个内部时钟信号的时钟产生单元和接收多个内部时钟信号的均衡接收单元和输入信号。 均衡接收单元可以在初始设置模式中确定偏移值和均衡系数，并且可以基于所确定的偏移值和均衡系数来调整接收的数据信号。

    Dividing circuit and phase locked loop using the same
    14.
    发明授权
    Dividing circuit and phase locked loop using the same 失效
    分频电路和锁相环使用相同

    公开(公告)号：US07843239B2

    公开(公告)日：2010-11-30

    申请号：US12318385

    申请日：2008-12-29

    申请人： Young-Soo Sohn ,  Kwang-II Park

    发明人： Young-Soo Sohn ,  Kwang-II Park

    IPC分类号： H03L7/06

    CPC分类号： G06G7/16 ,  H03K21/023 ,  H03L7/0891 ,  H03L7/183

    摘要： The PLL includes a selection signal generator configured to output a selection signal varying in response to a first clock signal, and a first dividing circuit configured to divide an externally input reference clock signal by a division ratio and output a first division signal. The first dividing circuit selects one of a plurality of edges of the reference clock signal applied for at least one cycle of the first division signal in response to the selection signal, and synchronizes and generates the first division signal on the basis of the selected edge of the reference clock signal. A second dividing circuit is configured to receive an output clock signal, divide the output clock signal by a division ratio, and output a second division signal. The second dividing circuit selects one of the edges of the reference clock signal applied for at least one cycle of the second division signal in response to the selection signal, and synchronizes and generates the second division signal on the basis of the selected edge of the reference clock signal. A synchronous signal output portion is configured to detect a phase difference between the first and second division signals, generate a control voltage corresponding to the phase difference, and output the output clock signal having a frequency corresponding to the control voltage.

    摘要翻译： PLL包括选择信号发生器，其被配置为输出响应于第一时钟信号而变化的选择信号;以及第一分频电路，被配置为将外部输入的参考时钟信号除以除法比，并输出第一除法信号。 第一分频电路响应于选择信号选择施加到第一分频信号的至少一个周期的参考时钟信号的多个边沿中的一个，并且基于所选择的边沿的同步并产生第一分频信号 参考时钟信号。 第二分频电路被配置为接收输出时钟信号，将输出时钟信号除以分频比，并输出第二除法信号。 第二分频电路响应于选择信号选择施加到第二分频信号的至少一个周期的参考时钟信号的边沿中的一个，并且基于参考的所选择的边沿同步并产生第二除法信号 时钟信号。 同步信号输出部被配置为检测第一和第二除法信号之间的相位差，产生与相位差对应的控制电压，并输出具有与控制电压对应的频率的输出时钟信号。

    Semiconductor memory device having power-saving effect
    15.
    发明授权
    Semiconductor memory device having power-saving effect 有权
    具有省电效果的半导体存储器件

    公开(公告)号：US08254201B2

    公开(公告)日：2012-08-28

    申请号：US12797791

    申请日：2010-06-10

    申请人： Young-Soo Sohn ,  Kwang-Il Park ,  Kyoung-Ho Kim ,  Seung-Jun Bae

    发明人： Young-Soo Sohn ,  Kwang-Il Park ,  Kyoung-Ho Kim ,  Seung-Jun Bae

    IPC分类号： G11C8/18 ,  G11C7/10

    CPC分类号： G11C7/22 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/18 ,  G11C2207/2227 ,  G11C2207/2272

    摘要： A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array.

    摘要翻译： 半导体存储器件包括存储单元阵列，控制器和数据输入/输出（I / O）单元。 存储单元阵列包括多个存储单元，并被配置为存储数据。 当半导体器件的写入延迟小于参考写入延迟并且在从半导体输出读取数据的禁用期间禁止写入时钟信号时，控制器被配置为响应于有效命令来使能写入时钟信号 设备。 数据I / O单元被配置为响应于写时钟信号接收数据并将数据输出到存储单元阵列。

    Semiconductor memory device having a latency controller
    16.
    发明授权
    Semiconductor memory device having a latency controller 有权
    具有等待时间控制器的半导体存储器件

    公开(公告)号：US08254184B2

    公开(公告)日：2012-08-28

    申请号：US12820364

    申请日：2010-06-22

    申请人： Young-Soo Sohn ,  Jeong-Don Lim ,  Kwang-Il Park

    发明人： Young-Soo Sohn ,  Jeong-Don Lim ,  Kwang-Il Park

    IPC分类号： G11C7/00 ,  G11C5/14 ,  G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/109 ,  G11C7/222 ,  G11C2207/2272

    摘要： A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.

    摘要翻译： 半导体存储器件包括提供省电效果的等待时间控制器。 等待时间控制器包括先进先出（FIFO）寄存器。 在应用读命令之后，当应用预充电命令或掉电命令时，等待时间控制器输出与所应用的读命令对应的等待时间信号，并阻止采样和发送时钟信号的应用到FIFO寄存器。

    Output driver and output driving method for enhancing initial output data using timing
    17.
    发明授权
    Output driver and output driving method for enhancing initial output data using timing 有权
    输出驱动器和输出驱动方法，用于使用定时来增强初始输出数据

    公开(公告)号：US07368949B2

    公开(公告)日：2008-05-06

    申请号：US11561765

    申请日：2006-11-20

    申请人： Young-Soo Sohn ,  Jung-Hwan Choi

    发明人： Young-Soo Sohn ,  Jung-Hwan Choi

    IPC分类号： H03K19/094 ,  H03D1/06

    CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1069

    摘要： An output driver for enhancing initial output data using timing includes a selection signal generation unit for generating a selection signal, a reference data generation unit for generating reference data, and a selection unit. The selection signal is activated at the transition point of the input data, generated after being maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number. The reference data is delayed from the input data by a delay time shorter than one bit period. The selection unit is driven to transition the logic state of the output data depending on the transition of the logic state of any one of the input data and the reference data in response to the selection signal.

    摘要翻译： 用于使用定时增强初始输出数据的输出驱动器包括用于产生选择信号的选择信号生成单元，用于产生参考数据的参考数据生成单元和选择单元。 选择信号在输入数据的转变点处被激活，在等于或大于预定持续时间数的位数周期中，在保持相同的逻辑状态之后产生。 参考数据从输入数据延迟一个比一个位周期短的延迟时间。 驱动选择单元，以响应于选择信号，根据输入数据和参考数据中的任何一个的逻辑状态的转变来转换输出数据的逻辑状态。

    Decision feedback equalization input buffer
    18.
    发明申请
    Decision feedback equalization input buffer 有权
    决策反馈均衡输入缓冲区

    公开(公告)号：US20050265440A1

    公开(公告)日：2005-12-01

    申请号：US11040808

    申请日：2005-01-21

    申请人： Young-Soo Sohn

    发明人： Young-Soo Sohn

    IPC分类号： H03L7/00 ,  H03K5/159 ,  H03L7/081

    CPC分类号： H03L7/0814 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03057

    摘要： In a decision feedback equalization (DFE) input buffer, timing and voltage errors, such as those caused by inter-symbol interference (ISI), are fully compensated. A variable equalizing coefficient is applied that accommodates, and compensates for, a range of timing errors TE or voltage errors VE that may be generated over a range of operating conditions. In this manner, accurate compensation is achieved, allowing for greater signal reliability and higher inter-circuit transfer rates. A decision feedback equalization (DFE) input buffer includes an equalizer that amplifies a difference in voltage level between an input signal and an oversampled signal in response to a variable equalizing control signal, the equalizer generating an amplified output signal. A sampling unit samples the amplified output signal in response to a sampling clock signal to generate the oversampled signal. A phase detector generates a timing control signal for controlling the timing of the activation of the sampling clock signal in response to a phase of the oversampled signal. An equalizing controller modifies the variable equalizing control signal in response to the timing control signal.

    摘要翻译： 在判决反馈均衡（DFE）输入缓冲器中，诸如由符号间干扰（ISI）引起的定时和电压误差被完全补偿。 施加可变均衡系数，其适应并补偿可能在一定范围的操作条件下产生的定时误差TE或电压误差VE的范围。 以这种方式，实现了精确的补偿，允许更大的信号可靠性和更高的电路间传输速率。 判决反馈均衡（DFE）输入缓冲器包括均衡器，该均衡器响应于可变均衡控制信号放大输入信号和过采样信号之间的电压电平差，均衡器产生放大的输出信号。 采样单元响应于采样时钟信号对放大的输出信号进行采样以产生过采样信号。 相位检测器响应于过采样信号的相位产生用于控制采样时钟信号的激活定时的定时控制信号。 均衡控制器响应于定时控制信号修改可变均衡控制信号。

    Decision feedback equalization input buffer
    19.
    发明授权
    Decision feedback equalization input buffer 有权
    决策反馈均衡输入缓冲区

    公开(公告)号：US07542507B2

    公开(公告)日：2009-06-02

    申请号：US11040808

    申请日：2005-01-21

    申请人： Young-Soo Sohn

    发明人： Young-Soo Sohn

    IPC分类号： H04B3/46 ,  H04B17/00 ,  H04Q1/20 ,  H03H7/30 ,  H03H7/40 ,  H03K5/159

    CPC分类号： H03L7/0814 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03057

    摘要： In a decision feedback equalization (DFE) input buffer, timing and voltage errors, such as those caused by inter-symbol interference (ISI), are fully compensated. A variable equalizing coefficient is applied that accommodates, and compensates for, a range of timing errors TE or voltage errors VE that may be generated over a range of operating conditions. In this manner, accurate compensation is achieved, allowing for greater signal reliability and higher inter-circuit transfer rates. A decision feedback equalization (DFE) input buffer includes an equalizer that amplifies a difference in voltage level between an input signal and an oversampled signal in response to a variable equalizing control signal, the equalizer generating an amplified output signal. A sampling unit samples the amplified output signal in response to a sampling clock signal to generate the oversampled signal. A phase detector generates a timing control signal for controlling the timing of the activation of the sampling clock signal in response to a phase of the oversampled signal. An equalizing controller modifies the variable equalizing control signal in response to the timing control signal.

    摘要翻译： 在判决反馈均衡（DFE）输入缓冲器中，诸如由符号间干扰（ISI）引起的定时和电压误差被完全补偿。 施加可变均衡系数，其适应并补偿可能在一定范围的操作条件下产生的定时误差TE或电压误差VE的范围。 以这种方式，实现了精确的补偿，允许更大的信号可靠性和更高的电路间传输速率。 判决反馈均衡（DFE）输入缓冲器包括均衡器，该均衡器响应于可变均衡控制信号放大输入信号和过采样信号之间的电压电平差，均衡器产生放大的输出信号。 采样单元响应于采样时钟信号对放大的输出信号进行采样以产生过采样信号。 相位检测器响应于过采样信号的相位产生用于控制采样时钟信号的激活定时的定时控制信号。 均衡控制器响应于定时控制信号修改可变均衡控制信号。

    Charge pump circuit for semiconductor memory device
    20.
    发明授权
    Charge pump circuit for semiconductor memory device 有权
    用于半导体存储器件的电荷泵电路

    公开(公告)号：US07456676B2

    公开(公告)日：2008-11-25

    申请号：US11350868

    申请日：2006-02-10

    申请人： Young-Soo Sohn

    发明人： Young-Soo Sohn

    IPC分类号： H03L5/00

    CPC分类号： G11C5/145 ,  H02M3/07 ,  H02M2001/009

    摘要： A charge pump circuit may include a cross-coupled load unit and a bias determination unit. The cross-coupled load unit may receive first and second input signals applied with mutually opposite phases to obtain a charge pumping. The cross-coupled load unit may have first and second output terminals that may be connected with transistors in a cascade connection structure. The bias determination unit may have a current mirror structure, and independently determine biases of a transistor among the cascade structure connected transistors in response to voltages of the first and second output terminals.

    摘要翻译： 电荷泵电路可以包括交叉耦合的负载单元和偏置确定单元。 交叉耦合负载单元可以接收以相互相反的相位施加的第一和第二输入信号以获得电荷泵浦。 交叉耦合负载单元可以具有可以以级联连接结构与晶体管连接的第一和第二输出端。 偏置确定单元可以具有电流镜结构，并且响应于第一和第二输出端子的电压独立地确定级联结构连接的晶体管中的晶体管的偏置。