公开(公告)号：US11881459B2

公开(公告)日：2024-01-23

申请号：US16867937

申请日：2020-05-06

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Lung Huang ,  Chee-Key Chung ,  Yuan-Hung Hsu ,  Chi-Jen Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/76804 ,  H01L23/5384 ,  H01L23/5386

Abstract: An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided.

公开(公告)号：US11610850B2

公开(公告)日：2023-03-21

申请号：US17160749

申请日：2021-01-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chih-Hsun Hsu ,  Chi-Jen Chen ,  Hsi-Chang Hsu ,  Yuan-Hung Hsu ,  Rui-Feng Tai ,  Don-Son Jiang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.

公开(公告)号：US20210280530A1

公开(公告)日：2021-09-09

申请号：US16876460

申请日：2020-05-18

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chi-Jen Chen ,  Chih-Hsun Hsu ,  Chee-Key Chung ,  Jia-Wei Pan ,  Chang-Fu Lin

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498

Abstract: Provided is an electronic package, including a multi-chip packaging body with a plurality of electronic elements and a stress buffer layer disposed on the multi-chip packaging body. The stress buffer layer is in contact with the plurality of electronic elements so as to cause stresses to be evenly distributed in the stress buffer layer instead of being concentrated in specific areas, thereby preventing structural stresses from being concentrated in corners of the electronic elements.

公开(公告)号：US20210082837A1

公开(公告)日：2021-03-18

申请号：US16867937

申请日：2020-05-06

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Lung Huang ,  Chee-Key Chung ,  Yuan-Hung Hsu ,  Chi-Jen Chen

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768

Abstract: An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided.