公开(公告)号：US20070184610A1

公开(公告)日：2007-08-09

申请号：US11733711

申请日：2007-04-10

申请人： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

发明人： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/40 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

公开(公告)号：US07605472B2

公开(公告)日：2009-10-20

申请号：US11706885

申请日：2007-02-15

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

摘要翻译： 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

公开(公告)号：US07279733B2

公开(公告)日：2007-10-09

申请号：US10799292

申请日：2004-03-12

申请人： Kyoung-woo Lee ,  Soo-geun Lee

发明人： Kyoung-woo Lee ,  Soo-geun Lee

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L21/76807 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.

摘要翻译： 提供了一种与金属 - 绝缘体 - 金属（MIM）电容器的双镶嵌互连及其制造方法。 在该结构中，在通孔级IMD上形成MIM电容器。 在形成通孔级IMD之后，当形成MIM电容器图形化的对准键时，形成通孔，以连接MIM电容器的下电极和配置在通孔级IMD下的互连。 此外，在双镶嵌工艺期间，MIM电容器的上电极直接连接到上金属互连。

公开(公告)号：US20070138642A1

公开(公告)日：2007-06-21

申请号：US11706885

申请日：2007-02-15

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

摘要翻译： 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

公开(公告)号：US07205666B2

公开(公告)日：2007-04-17

申请号：US11367790

申请日：2006-03-03

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

公开(公告)号：US20070298580A1

公开(公告)日：2007-12-27

申请号：US11897417

申请日：2007-08-30

申请人： Kyoung-woo Lee ,  Soo-geun Lee

发明人： Kyoung-woo Lee ,  Soo-geun Lee

IPC分类号： H01L21/20

CPC分类号： H01L21/76807 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.

摘要翻译： 提供了一种与金属 - 绝缘体 - 金属（MIM）电容器的双镶嵌互连及其制造方法。 在该结构中，在通孔级IMD上形成MIM电容器。 在形成通孔级IMD之后，当形成MIM电容器图形化的对准键时，形成通孔，以连接MIM电容器的下电极和配置在通孔级IMD下的互连。 此外，在双镶嵌工艺期间，MIM电容器的上电极直接连接到上金属互连。

公开(公告)号：US20060163736A1

公开(公告)日：2006-07-27

申请号：US11367790

申请日：2006-03-03

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

公开(公告)号：US07041592B2

公开(公告)日：2006-05-09

申请号：US10449973

申请日：2003-05-30

申请人： Jae-hak Kim ,  Soo-geun Lee ,  Kyung-woo Lee

发明人： Jae-hak Kim ,  Soo-geun Lee ,  Kyung-woo Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877

摘要： A method for forming a metal interconnection layer of a semiconductor device comprises forming a film including a material selective to a medium used in an ashing process on an interlayer insulating film. The method comprises transforming the film during the ashing process to form an interconnection pattern having a dual damascene structure. A dielectric material such as copper is deposited on the interconnection pattern, which is planarized through CMP, thereby forming a via contact having a single damascene structure without a recess therein.

摘要翻译： 一种用于形成半导体器件的金属互连层的方法包括在层间绝缘膜上形成包括对灰色处理中使用的介质有选择性的材料的膜。 该方法包括在灰化处理期间转换膜以形成具有双镶嵌结构的互连图案。 介电材料如铜沉积在互连图案上，其通过CMP平坦化，从而形成具有单个镶嵌结构的通孔接头，而其中没有凹槽。

公开(公告)号：US07037835B2

公开(公告)日：2006-05-02

申请号：US10744277

申请日：2003-12-23

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L21/44

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

公开(公告)号：US07951712B2

公开(公告)日：2011-05-31

申请号：US12556094

申请日：2009-09-09

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L21/44

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

摘要翻译： 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。