公开(公告)号：US20100240205A1

公开(公告)日：2010-09-23

申请号：US12720021

申请日：2010-03-09

申请人： Byoungkeun Son ,  Hansoo Kim ,  Jinho Kim ,  Kihyun Kim

发明人： Byoungkeun Son ,  Hansoo Kim ,  Jinho Kim ,  Kihyun Kim

IPC分类号： H01L21/28

CPC分类号： H01L21/28 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7841 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/7889

摘要： Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.

摘要翻译： 提供三维非易失性存储器件及其制造方法。 存储器件包括穿透层间绝缘层的半导体柱和交替层叠在衬底上并电连接到衬底的导电层和选择性地插入在半导体柱和导电层之间的浮置栅。 浮动栅极形成在导电层中的凹部中。

公开(公告)号：US08923053B2

公开(公告)日：2014-12-30

申请号：US14029100

申请日：2013-09-17

申请人： Jinman Han ,  Sunil Shim ,  Hansoo Kim ,  Jae-Hoon Jang ,  Byoungkeun Son

发明人： Jinman Han ,  Sunil Shim ,  Hansoo Kim ,  Jae-Hoon Jang ,  Byoungkeun Son

IPC分类号： G11C16/04 ,  G11C16/34 ,  H01L27/115 ,  G11C16/16 ,  G11C16/10 ,  H01L29/792

CPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased.

摘要翻译： 提供了一种操作包括基板的非易失性存储器件的方法和具有沿着垂直于衬底的方向堆叠的多个存储单元的存储器块。 该方法包括：响应于所选择的子块的读取，从所选择的存储器块的子块中读取选定的子块的数据并选择刷新所选存储块的每个子块，其中所选存储块的每个子块 被单独擦除。

公开(公告)号：US20110076819A1

公开(公告)日：2011-03-31

申请号：US12662187

申请日：2010-04-05

申请人： Jinho Kim ,  Byoungkeun Son ,  Hansoo Kim ,  Wonjun Lee ,  Daehyun Jang

发明人： Jinho Kim ,  Byoungkeun Son ,  Hansoo Kim ,  Wonjun Lee ,  Daehyun Jang

IPC分类号： H01L21/8239

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of fabricating a semiconductor memory device includes alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate, forming an active pattern penetrating the sacrificial layers and the insulating layers, continuously patterning the insulating layers and the sacrificial layers to form a trench, removing the sacrificial layers exposed in the trench to form recess regions exposing a sidewall of the active pattern, forming an information storage layer on the substrate, forming a gate conductive layer on the information storage layer, such that the gate conductive layer fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer, and performing an isotropic etch process with respect to the gate conductive layer to form gate electrodes in the recess regions, such that the gate electrodes are separated from each other.

摘要翻译： 一种制造半导体存储器件的方法包括在衬底上交替地和重复堆叠牺牲层和绝缘层，形成穿透牺牲层和绝缘层的有源图案，连续地图案化绝缘层和牺牲层以形成沟槽，去除 所述牺牲层暴露在所述沟槽中以形成露出所述有源图案的侧壁的凹陷区域，在所述衬底上形成信息存储层，在所述信息存储层上形成栅极导电层，使得所述栅极导电层填充所述凹部区域， 在沟槽中限定空区域，空区域被栅极导电层包围，并且相对于栅极导电层执行各向同性蚀刻处理，以在凹陷区域中形成栅电极，使得栅电极与每个栅电极分离 其他。

公开(公告)号：US20110204421A1

公开(公告)日：2011-08-25

申请号：US13102402

申请日：2011-05-06

申请人： Sukhun Choi ,  Kyunghyun Kim ,  ChangSup Mun ,  Byoungkeun Son

发明人： Sukhun Choi ,  Kyunghyun Kim ,  ChangSup Mun ,  Byoungkeun Son

IPC分类号： H01L29/41

CPC分类号： H01L27/11578 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

摘要： Provided are a three dimensional semiconductor memory device and a method of fabricating the same. The method includes forming a stepwise structure by using mask patterns and a sacrificial mask pattern formed on the mask patterns as a consumable etch mask.

公开(公告)号：US09947686B2

公开(公告)日：2018-04-17

申请号：US15456841

申请日：2017-03-13

申请人： Byoungkeun Son ,  Yoocheol Shin ,  Changhyun Lee ,  Hyunjung Kim ,  Chung-Il Hyun

发明人： Byoungkeun Son ,  Yoocheol Shin ,  Changhyun Lee ,  Hyunjung Kim ,  Chung-Il Hyun

IPC分类号： H01L29/788 ,  H01L27/11582 ,  H01L27/11565 ,  H01L21/28 ,  H01L27/1157

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction.

公开(公告)号：US08872183B2

公开(公告)日：2014-10-28

申请号：US13366057

申请日：2012-02-03

申请人： Sung-Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

发明人： Sung-Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

IPC分类号： H01L29/04 ,  H01L21/822 ,  H01L27/115 ,  H01L27/06

CPC分类号： H01L27/11582 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556 ,  H01L29/4232 ,  H01L29/42372

摘要： Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

摘要翻译： 提供三维半导体器件。 三维半导体器件包括衬底，衬底上的缓冲层。 缓冲层包括具有相对于衬底的蚀刻选择性的材料。 在与衬底相对的缓冲层上提供包括交替绝缘图案和导电图案的多层堆叠。 一个或多个有源图案分别延伸穿过多层堆叠的交替绝缘图案和导电图案并进入缓冲层。 还讨论了相关的制造方法。

公开(公告)号：US20140042520A1

公开(公告)日：2014-02-13

申请号：US14057380

申请日：2013-10-18

申请人： Changhyun Lee ,  Byoungkeun Son ,  Hyejin Cho

发明人： Changhyun Lee ,  Byoungkeun Son ,  Hyejin Cho

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7926

摘要： Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

摘要翻译： 三维（3D）非易失性存储器件包括其中具有第二导电类型（例如，P型）的阱区和在该区域上具有第一导电类型（例如，N型）的公共源极区的衬底。 凹部部分（或完全）延伸穿过公共源区域。 衬底上的垂直堆叠的非易失性存储器单元包括间隔开的栅电极的垂直堆叠和垂直有源区，该垂直有源区延伸在间隔开的栅电极的垂直堆叠的侧壁上并在凹槽的侧壁上延伸。 栅极电介质层在相互间隔开的栅电极的垂直叠层和垂直有源区之间延伸。 栅极电介质层可以包括隧道绝缘层，电荷存储层，相对高的带隙势垒介电层和具有相对高的介电强度的阻挡绝缘层的复合材料。

公开(公告)号：US09536895B2

公开(公告)日：2017-01-03

申请号：US14657849

申请日：2015-03-13

申请人： Changhyun Lee ,  Chanjin Park ,  Byoungkeun Son ,  Sung-Il Chang

发明人： Changhyun Lee ,  Chanjin Park ,  Byoungkeun Son ,  Sung-Il Chang

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/0649 ,  H01L29/7926

摘要： A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

摘要翻译： 三维半导体器件包括下结构的上结构，上结构包括导电图案，通过上结构连接到下结构的半导体图案，以及半导体图案和上结构之间的绝缘间隔物，底部 绝缘间隔物的表面位于等于或高于下部结构的最上表面的垂直水平。

公开(公告)号：US08891315B2

公开(公告)日：2014-11-18

申请号：US13827674

申请日：2013-03-14

申请人： ChangHyun Lee ,  Byoungkeun Son

发明人： ChangHyun Lee ,  Byoungkeun Son

IPC分类号： G11C11/34 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3445 ,  G11C16/0483 ,  G11C16/16

摘要： A method of erasing a nonvolatile memory device, which includes a plurality of memory blocks each formed of a plurality of strings, includes applying an erase voltage to a well of a selected memory block of the memory blocks, each memory block including at least two dummy cells located between a string or ground selection transistor and memory cells; and applying or inducing different levels of voltages to respective gates of the at least two dummy cells.

摘要翻译： 一种擦除非易失性存储器件的方法，包括由多个串组成的多个存储块，包括将擦除电压施加到存储块的选定存储块的阱中，每个存储块包括至少两个虚拟 位于串或地选择晶体管和存储单元之间的单元; 以及向所述至少两个虚拟单元的相应门施加或诱导不同电平的电压。

公开(公告)号：US08643080B2

公开(公告)日：2014-02-04

申请号：US13217416

申请日：2011-08-25

申请人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

发明人： Changhyun Lee ,  Byoungkeun Son ,  Youngwoo Park

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L21/06 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor devices. The devices may include gap-fill insulating patterns configured to upwardly extend from a substrate and an electrode structure defined by sidewalls of the gap-fill insulating patterns. Vertical structures may be provided between adjacent ones of the gap-fill insulating patterns to penetrate the electrode structure, and the vertical structures may include first and second rows of the vertical structures. A separation pattern may be provided between the first and second rows of vertical structures and include a separation semiconductor layer. The separation pattern extends along a direction parallel to the first and second rows of vertical structures.

摘要翻译： 提供三维半导体器件。 这些装置可以包括配置成从基板向上延伸的间隙填充绝缘图案和由间隙填充绝缘图案的侧壁限定的电极结构。 可以在相邻的间隙填充绝缘图案之间提供垂直结构以穿透电极结构，并且垂直结构可以包括垂直结构的第一行和第二行。 可以在第一和第二排垂直结构之间提供分离图案，并且包括分离半导体层。 分离图案沿着平行于第一和第二排垂直结构的方向延伸。