公开(公告)号：US20220254735A1

公开(公告)日：2022-08-11

申请号：US17679082

申请日：2022-02-24

Applicant: Texas Instruments Incorporated

Inventor： Jaimal Mallory Williamson ,  Guangxu Li

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

公开(公告)号：US20250105104A1

公开(公告)日：2025-03-27

申请号：US18475563

申请日：2023-09-27

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Rey Javier ,  Guangxu Li ,  Enis Tuncer

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: An electronic device includes a package structure having four lateral corners, a semiconductor die at least partially enclosed inside the package structure and attached to a die attach pad, conductive leads at least partially exposed outside the package structure along the four lateral sides, a first one of the conductive leads electrically connected to the semiconductor die, an instance of a first conductive feature partially exposed outside the package structure at each of the corners, and an instance of a second conductive feature partially exposed outside the package structure and contacting a respective instance of the first conductive feature at each of the corners, the instance of the second conductive feature exposed outside the package structure along the first side.

公开(公告)号：US11270955B2

公开(公告)日：2022-03-08

申请号：US16205436

申请日：2018-11-30

Applicant: Texas Instruments Incorporated

Inventor： Jaimal Mallory Williamson ,  Guangxu Li

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.

公开(公告)号：US10748863B2

公开(公告)日：2020-08-18

申请号：US15835197

申请日：2017-12-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaimal Mallory Williamson ,  Guangxu Li

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29

Abstract: A semiconductor device includes a first body having a first coefficient of thermal expansion (CTE) and a first surface, a third body having a third CTE and a third surface facing the first surface, and a fourth surface at an angle with respect to the third surface defining an edge of the third body, and a second body having a second CTE higher than the first and the third CTE, the second body contacting the first and the third surfaces. A post having a fourth CTE lower than the second CTE, transects the second body and contacts the edge.

公开(公告)号：US20200251436A1

公开(公告)日：2020-08-06

申请号：US16778250

申请日：2020-01-31

Applicant: Texas Instruments Incorporated

Inventor： Jaimal Mallory Williamson ,  Guangxu Li

IPC: H01L23/00 ,  H01L21/48

Abstract: A described example includes a package substrate having an array of die pads arranged in rows and columns on a die mount surface, and having an opposing board side surface; a solder mask layer overlying the die mount surface; a first plurality of solder mask defined openings in the solder mask layer at die pad locations, the solder mask defined openings exposing portions of a surface of corresponding die pads, the surface facing away from the package substrate; and at least one non-solder mask defined opening in the solder mask layer at a die pad location, exposing the entire surface of the die pad and sidewalls of the die pad at the non-solder mask defined opening.

公开(公告)号：US20180190606A1

公开(公告)日：2018-07-05

申请号：US15835197

申请日：2017-12-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaimal Mallory Williamson ,  Guangxu Li

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29

Abstract: A semiconductor device includes a first body having a first coefficient of thermal expansion (CTE) and a first surface, a third body having a third CTE and a third surface facing the first surface, and a fourth surface at an angle with respect to the third surface defining an edge of the third body, and a second body having a second CTE higher than the first and the third CTE, the second body contacting the first and the third surfaces. A post having a fourth CTE lower than the second CTE, transects the second body and contacts the edge.