公开(公告)号：US12028066B2

公开(公告)日：2024-07-02

申请号：US18307994

申请日：2023-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kyoung Min Lee ,  James M. Walden ,  Brian Linehan ,  Yang Zhang

IPC: H03K19/003 ,  H03K17/081 ,  H03K17/0812 ,  H03K17/16

CPC classification number: H03K19/00384 ,  H03K17/08104 ,  H03K17/0812 ,  H03K17/08122 ,  H03K17/163 ,  H03K17/166

Abstract: In a transistor turnoff system, a transistor control circuit is configured to adjust a control voltage at a transistor control output responsive to a comparison signal at a control input. The control voltage has a slew rate. A comparator has a comparator output and first and second comparator inputs. The first comparator input is coupled to the transistor control output. The comparator is configured to: provide the comparison signal at the comparator output based on a reference voltage at the second comparator input; and deactivate the transistor control circuit by changing a state of the comparison signal responsive to the control voltage falling below the reference voltage. A slew-rate compensator is configured to increase the reference voltage by a compensation voltage that compensates for a time delay of the comparator or the transistor control circuit. The compensation voltage is proportional to the slew rate.

公开(公告)号：US20210119627A1

公开(公告)日：2021-04-22

申请号：US16801746

申请日：2020-02-26

Applicant: Texas Instruments Incorporated

Inventor： Kyoung Min Lee ,  Satish Kumar Vemuri ,  James Michael Walden

IPC: H03K17/567 ,  H02P27/08 ,  H02M7/5387 ,  H02M1/08

Abstract: Gate driver bootstrap circuits and related methods are disclosed. An example gate driver stage includes a first terminal and a second terminal, the first terminal to be coupled to a capacitor, the capacitor and the second terminal to be coupled to a gate terminal of a power transistor, a gate driver coupled to the first terminal and the second terminal, and a bootstrap circuit coupled to the first terminal, the second terminal, and the gate driver, the bootstrap circuit including a control stage circuit having an output and a first transistor having a first gate terminal and a first current terminal, the first gate terminal coupled to the output, the first current terminal coupled to the first terminal.