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公开(公告)号:US20090235028A1
公开(公告)日:2009-09-17
申请号:US11720751
申请日:2006-03-22
申请人: Keisuke Kaneko
发明人: Keisuke Kaneko
CPC分类号: G06F12/0864 , G06F12/084 , G06F12/121 , G06F12/126 , G06F12/128 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要: An object of the present invention is to reduce power consumption accompanying a cache hit/miss determination. To achieve this object, when accessing a cache memory provided with a means for setting whether a cache refill to each way in the cache memory is allowed for each CPU or each thread, first, a first cache hit/miss determination is performed only on the way for which a refill is set to be allowed (Steps 2-1 and 2-2), and if the first cache hit/miss determination results in a cache hit, the access is ended (Step 2-6). In the case of a cache miss, the way for which a refill is not set to be allowed is accessed (Step 2-3), or a second hit/miss determination is performed by accessing all the ways (Step 2-4).
摘要翻译: 本发明的目的是降低伴随高速缓存命中/错误确定的功耗。 为了实现该目的,当访问具有用于设置是否允许针对每个CPU或每个线程的高速缓冲存储器中的每个路径的高速缓存重新填充的装置的缓存存储器时,首先,仅在 设置补充的方式(步骤2-1和2-2),并且如果第一高速缓存命中/未命中确定导致高速缓存命中,则访问结束(步骤2-6)。 在缓存未命中的情况下,访问不设置允许的方式(步骤2-3),或者通过访问所有方式执行第二命中/未命中确定(步骤2-4)。