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107 条记录 (耗时 0.027 秒)

    Method of resource arbitration
    11.
    发明授权
    Method of resource arbitration 失效
    资源仲裁方法

    公开(公告)号：US07099975B2

    公开(公告)日：2006-08-29

    申请号：US10730952

    申请日：2003-12-09

    申请人： Jeffrey Douglas Brown ,  Scott Douglas Clark ,  Charles Ray Johns ,  Takeshi Yamazaki

    发明人： Jeffrey Douglas Brown ,  Scott Douglas Clark ,  Charles Ray Johns ,  Takeshi Yamazaki

    IPC分类号： G06F12/00

    CPC分类号： G06F13/3625

    摘要： An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.

    摘要翻译： 一种改进的资源仲裁方法和装置。 定义了四个优先级，管理高（MH），管理低（ML），机会高（OH）和机会主义低（OL）。 优先级分配给每个资源访问请求。 为每个资源创建访问请求集中器（ARC），通过该资源访问资源。 在优先级顺序为MH，ML，OH和OL的每个ARC中选择访问请求。 如果OH优先级资源访问请求被锁定，优先级顺序将按照优先级的降序暂时更改为OH，OL，MH和ML。 如果OL优先级资源访问请求被锁定，优先级顺序将按照优先级的降序临时更改为MH，OL，OH和ML。

    Method to provide cache management commands for a DMA controller
    14.
    发明授权
    Method to provide cache management commands for a DMA controller 失效
    为DMA控制器提供高速缓存管理命令的方法

    公开(公告)号：US07657667B2

    公开(公告)日：2010-02-02

    申请号：US10809553

    申请日：2004-03-25

    申请人： Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  Thuong Quang Truong

    发明人： Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  Thuong Quang Truong

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28 ,  G06F12/0835 ,  G06F12/0837 ,  G06F12/0862

    摘要： The present invention provides a method and a system for providing cache management commands in a system supporting a DMA mechanism and caches. A DMA mechanism is set up by a processor. Software running on the processor generates cache management commands. The DMA mechanism carries out the commands, thereby enabling the software program management of the caches. The commands include commands for writing data to the cache, loading data from the cache, and for marking data in the cache as no longer needed. The cache can be a system cache or a DMA cache.

    摘要翻译： 本发明提供了一种用于在支持DMA机制和高速缓存的系统中提供高速缓存管理命令的方法和系统。 DMA机制由处理器设置。 处理器上运行的软件会生成缓存管理命令。 DMA机制执行命令，从而实现高速缓存的软件程序管理。 这些命令包括用于将数据写入缓存的命令，从高速缓存加载数据，以及用于在不再需要的情况下将数据标记在缓存中。 缓存可以是系统缓存或DMA高速缓存。

    System and method for a configurable interface controller
    15.
    发明授权
    System and method for a configurable interface controller 有权
    可配置接口控制器的系统和方法

    公开(公告)号：US08108564B2

    公开(公告)日：2012-01-31

    申请号：US10697903

    申请日：2003-10-30

    申请人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

    发明人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

    IPC分类号： G06F3/00

    CPC分类号： G06F3/1423 ,  G06F3/1454 ,  G09G5/14 ,  G09G2360/121 ,  G09G2370/04

    摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

    摘要翻译： 灵活的输入/输出控制器逻辑与现有的输入/输出控制器（IOC）进行接口，以便配置向国际奥委会发送和接收的数据量。 灵活的I / O接口以特定组件确定的速率从组件接收数据。 然后，灵活的I / O接口以适合于I / O控制器的速率将接收的数据馈送到传统的I / O控制器。 因此，保持与各个I / O控制器的接口。 灵活的I / O逻辑平衡多个独立I / O控制器之间的带宽，以便更好地利用整个系统I / O带宽。 在一个实施例中，在系统构建期间确定由灵活I / O逻辑管理的I / O配置，而在另一实施例中，在系统初始化期间设置I / O配置。

    Non-Homogeneous Multi-Processor System With Shared Memory
    16.
    发明申请
    Non-Homogeneous Multi-Processor System With Shared Memory 审中-公开
    具有共享内存的非均匀多处理器系统

    公开(公告)号：US20080162877A1

    公开(公告)日：2008-07-03

    申请号：US12049324

    申请日：2008-03-15

    申请人： Erik Richter Altman ,  Peter George Capek ,  Michael Karl Gschwind ,  Charles Ray Johns ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle ,  Sumedh W. Sathaye ,  John-David Wellman ,  Ravi Nair

    发明人： Erik Richter Altman ,  Peter George Capek ,  Michael Karl Gschwind ,  Charles Ray Johns ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  James Allan Kahle ,  Sumedh W. Sathaye ,  John-David Wellman ,  Ravi Nair

    IPC分类号： G06F15/76 ,  G06F9/30

    CPC分类号： H04L63/168 ,  H04L67/10

    摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

    摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。

    System and method for identifying and accessing streaming data in a locked portion of a cache
    20.
    发明授权
    System and method for identifying and accessing streaming data in a locked portion of a cache 失效
    用于在高速缓存的锁定部分中识别和访问流数据的系统和方法

    公开(公告)号：US06961820B2

    公开(公告)日：2005-11-01

    申请号：US10366440

    申请日：2003-02-12

    申请人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David J. Shippy ,  Thuong Quang Truong

    发明人： Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Peichun Peter Liu ,  David J. Shippy ,  Thuong Quang Truong

    IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/12

    CPC分类号： G06F12/126

    摘要： A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.

    摘要翻译： 提供了一种系统和方法，用于在计算机系统中用高速缓存高效地处理数据。 计算机系统具有处理器，缓存和系统存储器。 处理器发出流数据的数据请求。 流数据具有一个或多个小数据部分。 系统存储器与处理器通信。 系统存储器具有用于存储流数据的特定区域。 缓存耦合到处理器。 高速缓存具有为流数据锁定的预定义区域。 高速缓存控制器耦合到高速缓存，并且与处理器和系统存储器通信，以将流式数据的至少一个小数据部分从系统存储器的特定区域发送到高速缓存的预定义区域 在缓存的预定义区域中没有找到小数据部分。