Vector data processing system for indirect address instructions
    11.
    发明授权
    Vector data processing system for indirect address instructions 失效
    用于间接地址指令的矢量数据处理系统

    公开(公告)号:US4665479A

    公开(公告)日:1987-05-12

    申请号:US654591

    申请日:1984-09-26

    申请人: Yuji Oinaga

    发明人: Yuji Oinaga

    CPC分类号: G06F15/8084

    摘要: A vector data processing system includes at least an A-access pipeline (27) and a B-access pipeline (28) between a main storage unit (4) and vector registers (21). Associated with the A-access pipeline (27) are a write port (WA) and a read port (RA) selectively connected to the vector registers (21). Associated with the B-access pipeline (28) are a write port (WB) and a read port (RB) selectively connected to the vector registers (21). An additional read port (IA) is linked between the read port (RB) of the B-access pipeline (28) and the address input side of the A-access pipeline (27). When an indirect address load/store instruction is carried out for the A-access pipeline (27), an indirect address is generated from the vector registers (21) via the read port (RB) of the B-access pipeline (28) and the additional read port (IA).

    摘要翻译: 矢量数据处理系统至少包括主存储单元(4)和矢量寄存器(21)之间的A访问流水线(27)和B访问流水线(28)。 与A访问管道(27)相关联的是写入端口(WA)和选择性地连接到向量寄存器(21)的读端口(RA)。 与B访问流水线(28)相关联的是写入端口(WB)和选择性地连接到向量寄存器(21)的读端口(RB)。 另外的读取端口(IA)链接在B访问流水线(28)的读取端口(RB)和A访问流水线(27)的地址输入端之间。 当对A访问流水线(27)执行间接寻址加载/存储指令时,通过B访问流水线(28)的读端口(RB)从向量寄存器(21)生成间接地址, 附加读端口(IA)。