公开(公告)号：US20250017003A1

公开(公告)日：2025-01-09

申请号：US18230174

申请日：2023-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Yih Chen ,  Yi-Wen Chen ,  Wei-Chung Sun

IPC: H10B20/00 ,  G06F21/75

Abstract: A method for physically unclonable function through gate height tuning is provided in the present invention, including steps of forming a high-k dielectric layer and a dummy silicon layer on a semiconductor substrate, removing the dummy silicon layer, forming a work function layer and a metal filling layer on the high-k dielectric layer, and performing a CMP process to remove the metal filling layer, so as to form metal gates with heights lower than a critical gate height, and using the metal gates to manufacture PIO pairs in an internal bias generator. Since the height of metal gates is lower than the critical gate height, a local threshold voltage mismatching of the programmed I/O (PIO) pairs becomes larger, so as to achieve random code generation in physically unclonable function (PUF).

公开(公告)号：US20240413017A1

公开(公告)日：2024-12-12

申请号：US18220839

申请日：2023-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Ya-Ting Hu ,  Wei-Che Chen ,  Chang-Yih Chen ,  Kun-Szu Tseng ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, forming fin-shaped structures on the LV region, forming an insulating layer between the fin-shaped structures, forming a hard mask on the LV region, and then performing a thermal oxidation process to form a gate dielectric layer on the MV region. Preferably, a hump is formed on the substrate surface of the MV region after the hard mask is removed, in which the hump further includes a first hump adjacent to one side of the substrate on the MV region and a second hump adjacent to another side of the substrate on the MV region.