公开(公告)号：US20240290875A1

公开(公告)日：2024-08-29

申请号：US18656574

申请日：2024-05-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Kuo-Yu Liao

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66462

Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.

公开(公告)号：US20240234559A1

公开(公告)日：2024-07-11

申请号：US18614735

申请日：2024-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Kuo-Yu Liao

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a buffer layer on the substrate, forming a mesa isolation on the HEMT region, forming a HEMT on the mesa isolation, and then forming a capacitor on the capacitor region. Preferably, a bottom electrode of the capacitor contacts the buffer layer directly.

公开(公告)号：US11973133B2

公开(公告)日：2024-04-30

申请号：US18144822

申请日：2023-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Kuo-Yu Liao

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a first mesa isolation on the HEMT region and a second mesa isolation on the capacitor region, forming a HEMT on the first mesa isolation, and then forming a capacitor on the second mesa isolation.

公开(公告)号：US20220181505A1

公开(公告)日：2022-06-09

申请号：US17145416

申请日：2021-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Li Lin ,  Wei-Da Lin ,  Cheng-Guo Chen ,  Ta-Kang Lo ,  Yi-Chuan Chen ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Kuan-Ting Lu ,  Kuo-Yu Liao

IPC: H01L29/94 ,  H01L29/66

Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

公开(公告)号：US10777508B2

公开(公告)日：2020-09-15

申请号：US15347757

申请日：2016-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Kang ,  Sheng-Yuan Hsueh ,  Yi-Chung Sheng ,  Kuo-Yu Liao ,  Shu-Hung Yu ,  Hung-Hsu Lin ,  Hsiang-Hung Peng

IPC: H01L23/544 ,  H01L27/092 ,  H01L27/02 ,  G03F9/00 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. The first gate structures straddle the first active region and the second active region. The first conductive structures are disposed on the first active region, the second active region, and two opposite sides of the first gate structures.