公开(公告)号：US20230137853A1

公开(公告)日：2023-05-04

申请号：US17513851

申请日：2021-10-28

Applicant: United Microelectronics Corp.

Inventor： Zong-Han Lin

IPC: H01L27/24 ,  H01L45/00

Abstract: The invention provides a RRAM structure, which includes a substrate, a high voltage transistor, and a RRAM cell. The high voltage transistor includes a drift region, a gate structure, a source region, a drain region, and an isolation structure. The drift region is located in the substrate. The gate structure is located on the substrate and on a portion of the drift region. The source region and the drain region are located in the substrate on two sides of the gate structure. The drain region is located in the drift region. The isolation structure is located in the drift region and between the gate structure and the drain region. The RRAM cell includes a first electrode, a resistive switching layer, and a second electrode sequentially located on the drain region. The RRAM cell is electrically connected to the high voltage transistor.

公开(公告)号：US20230130955A1

公开(公告)日：2023-04-27

申请号：US17533056

申请日：2021-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zong-Han Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: A lateral diffused metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a second fin-shaped structure adjacent to the first fin-shaped structure, a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, a first gate structure on the first fin-shaped structure, a second gate structure on the second fin-shaped structure, and an air gap between the first gate structure and the second gate structure.

公开(公告)号：US11637200B2

公开(公告)日：2023-04-25

申请号：US17378820

申请日：2021-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zong-Han Lin ,  Yi-Han Ye

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

Abstract: A power semiconductor device includes a substrate, a first well, a second well, a drain, a source, a first gate structure, a second gate structure and a doping region. The first well has a first conductivity and extends into the substrate from a substrate surface. The second well has a second conductivity and extends into the substrate from the substrate surface. The drain has the first conductivity and is disposed in the first well. The source has the first conductivity and is disposed in the second well. The first gate structure is disposed on the substrate surface and at least partially overlapping with the first well and second well. The second gate structure is disposed on the substrate surface and overlapping with the second well. The doping region has the first conductivity, is disposed in the second well and connects the first gate structure with the second gate structure.