公开(公告)号：US20080116547A1

公开(公告)日：2008-05-22

申请号：US11600919

申请日：2006-11-17

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/495

CPC分类号： H01L23/16 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An IC package keeping the attachment level of leads on chip during molding process, mainly comprises a plurality of leads of a Lead-On-Chip (LOC) leadframe, a chip adhered under the leads, a plurality of bonding wires electrically connecting the chip to the leads, a plurality of first supporting columns disposed above some of the leads, a plurality of second supporting columns disposed under the some of the leads and a molding compound. The molding compound encapsulates the chip, the bonding wires, inner portions of the leads and sides of the first and second supporting columns. Therein, the first and second supporting columns are longitudinally corresponding to each other and adjacent the chip. The thickness including one of the first supporting columns, a corresponding one of the second supporting columns and one of the leads disposed corresponding to the selected first supporting column and the selected second supporting column is approximately as same as that of the molding compound. By means of the supporting columns in the package, it is able to prevent the problems of chip displacement during molding process and exposure of chip backside or the bonding wires.

摘要翻译： 一种在成型工艺中保持芯片引线附着水平的IC封装，主要包括芯片上引线框架（LOC）的多个引线，引线下方的芯片，将芯片电连接到 引线，设置在一些引线上方的多个第一支撑柱，设置在一些引线下方的多个第二支撑柱和模制化合物。 模塑料封装芯片，接合线，引线的内部和第一和第二支撑柱的侧面。 其中，第一和第二支撑柱纵向对应并且与芯片相邻。 包括第一支撑柱中的一个，相应的一个第二支撑柱和与所选择的第一支撑柱相对应设置的一个引线和所选择的第二支撑柱之间的厚度大致与模塑料的相同。 通过封装中的支撑柱，可以防止模制过程中芯片位移的问题和芯片背面或接合线的暴露。

公开(公告)号：US20070252252A1

公开(公告)日：2007-11-01

申请号：US11413014

申请日：2006-04-28

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/02

CPC分类号： H01L23/49816 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/094 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012

摘要： A PCB for mounting IC package is designed with dummy solder pads. Dummy solder pastes will spread on the dummy solder pads after screen printing process of solder paste. A substrate for a package of IC is designed with or without dummy solder pads. After mounting the package of IC onto the PCB, the dummy solder paste may or may not solder to the substrate of the package of IC. When the package of IC suffers external force, the dummy solder pastes can help provide supporting for the package of IC and increase the mechanical strength to avoid package or IC crack.

摘要翻译： 用于安装IC封装的PCB设计有虚拟焊盘。 在焊膏丝网印刷工艺之后，虚拟焊膏将在虚拟焊盘上铺展。 用于封装IC的衬底被设计为具有或不具有虚拟焊盘。 将IC封装安装到PCB上后，虚拟焊膏可能会焊接到IC封装的衬底上，也可能不会焊接到IC封装的衬底上。 当IC封装受到外力时，虚拟焊膏可以帮助提供对IC封装的支持，并增加机械强度以避免封装或IC裂纹。

公开(公告)号：US08420437B1

公开(公告)日：2013-04-16

申请号：US13311063

申请日：2011-12-05

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L9/00 ,  H01L21/00

CPC分类号： H01L23/552 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Disclosed is a method for forming an EMI shielding layer on all surfaces of a semiconductor package in order to enhance EMI shielding effect on all surfaces and to prevent electrical short to external terminals of the semiconductor package. According to the method, a temporary protective layer is formed on the external terminals where the temporary protective layer is further in contact with a plurality of annular surface regions of the semiconductor package surrounding and adjacent to the external terminals. Then, the EMI shielding layer is formed on the top surface, the bottom surface and the side surfaces of the semiconductor package without forming on the external terminals.

摘要翻译： 公开了一种用于在半导体封装的所有表面上形成EMI屏蔽层的方法，以便增强对所有表面的EMI屏蔽效果，并防止对半导体封装的外部端子的电短路。 根据该方法，在外部端子上形成临时保护层，其中临时保护层与外部端子周围和邻近的半导体封装体的多个环形表面区域进一步接触。 然后，EMI屏蔽层形成在半导体封装的顶表面，底表面和侧表面上，而不形成在外部端子上。

公开(公告)号：US07902663B2

公开(公告)日：2011-03-08

申请号：US12118052

申请日：2008-05-09

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/12

CPC分类号： H01L23/13 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package with enhanced mobility of ball terminals is revealed. A chip is attached to the substrate by a die-attaching material where the substrate has at least a stepwise depression on the covered surface to make the substrate thickness be stepwise decreased from a central line of the die-attaching area toward two opposing sides of the substrate. The die-attaching material is filled in the stepwise depression. Therefore, the thickness of the die-attaching material under cross-sectional corner(s) of the chip becomes thicker so that a row of the ball terminals away from the central line of the die-attaching area can have greater mobility without changing the appearance, dimensions, thicknesses of the semiconductor package, nor the placing plane of the ball terminals. Accordingly, the row of ball terminals located adjacent the edges or corners of the semiconductor package can withstand larger stresses without ball cracks nor ball drop. The stepwise depression can accommodate the die-attaching material to control bleeding contaminations.

摘要翻译： 显示出具有增强的球端子移动性的半导体封装。 芯片通过芯片附着材料附着到基板上，其中基板在被覆表面上具有至少一个阶梯式凹陷，以使基板厚度从模具安装区域的中心线逐渐减小到 基质。 模具附着材料填充在阶梯式凹陷中。 因此，芯片的截面角下的模具安装材料的厚度变厚，使得离开模具安装区域的中心线的一排球端子能够在不改变外观的情况下具有更大的移动性 半导体封装的尺寸，厚度，以及球形端子的放置平面。 因此，位于半导体封装的边缘或角落附近的一排球端子可以承受较大的应力，而不会产生球裂纹或球掉落。 阶梯式凹陷可以容纳模具附着材料以控制出血污染。

公开(公告)号：US07696618B2

公开(公告)日：2010-04-13

申请号：US11984782

申请日：2007-11-21

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/02

CPC分类号： H01L23/13 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device having package-on-package (POP) configuration, primarily comprises a plurality of vertically stacked semiconductor packages and a plurality of electrical connecting components such as solder paste to electrically connect the external terminals of the semiconductor packages such as external leads of leadframes. Each semiconductor package has an encapsulant to encapsulate at least a chip where the encapsulant is movable with respect to the electrical connecting components to absorb the stresses between the vertically stacked semiconductor packages. In one embodiment, a stress-releasing layer is interposed between the vertically stacked semiconductor packages.

摘要翻译： 具有封装封装（POP）配置的半导体器件主要包括多个垂直堆叠的半导体封装和多个电连接部件，例如焊膏，以电连接半导体封装的外部端子，例如引线框的外部引线 。 每个半导体封装具有密封剂以封装至少一个芯片，其中密封剂相对于电连接部件可移动，以吸收垂直堆叠的半导体封装之间的应力。 在一个实施例中，应力释放层介于垂直堆叠的半导体封装之间。

公开(公告)号：US07633143B1

公开(公告)日：2009-12-15

申请号：US12234894

申请日：2008-09-22

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/49503 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package with multiple chips side-by-side disposed on a leadframe is revealed, primarily comprising a plurality of leads of a leadframe, a first chip, a second chip, and an encapsulant to encapsulate the chips where the chip thickness of the second chip is larger than the one of the first chip. The first chip and the second chip are individually disposed on a first die-attaching area and on a second die-attaching area of the leads or a die pad of the leadframe. The second die-attaching area is downset relative to the first die-attaching area in a manner that a bottom surface of the encapsulant is closer to the second die-attaching areas than to the first die-attaching areas. Therefore, when chips with different thicknesses are side-by-side disposed, there is no unbalanced mold flow nor package warpage issue.

摘要翻译： 揭示了具有并排设置在引线框架上的多个芯片的半导体封装，主要包括引线框架，第一芯片，第二芯片和密封剂的多个引线，以封装芯片，其中第二 芯片大于第一芯片之一。 第一芯片和第二芯片分别设置在引线框架的第一管芯附接区域和引线的第二管芯附着区域或管芯焊盘上。 第二管芯安装区域相对于第一管芯附着区域以与第一管芯附着区域相比更靠近第二管芯附着区域的方式下降。 因此，当并排布置具有不同厚度的芯片时，没有不平衡的模具流动和封装翘曲问题。

公开(公告)号：US20090302441A1

公开(公告)日：2009-12-10

申请号：US12133892

申请日：2008-06-05

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L23/49555 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A Chip-On-Lead (COL) multi-chip package is revealed, primarily comprising a plurality of leads, a first chip disposed on the first leads, one or more second chips stacked on the first chip, and an encapsulant. The leads have a plurality of internal leads encapsulated inside the encapsulant where the internal leads are fully formed on a downset plane toward and parallel to a bottom surface of the encapsulant. The height between the internal leads to a top surface of the encapsulant is three times or more greater than the height between the internal leads and the bottom surface. Since the number and the thickness of the second chips is under controlled, tile thickness between the top surface of the encapsulant and the most adjacent one of the second chips is about the same as the one between the internal leads and the bottom surface of the encapsulant. Therefore, the internal leads of the leads without downset bends in the encapsulant can balance the upper and lower mold flows and carry more chips without shifting nor tilting.

摘要翻译： 揭示了芯片引线（COL）多芯片封装，主要包括多个引线，设置在第一引线上的第一芯片，堆叠在第一芯片上的一个或多个第二芯片和密封剂。 引线具有封装在密封剂内部的多个内部引线，其中内部引线完全形成在朝向并平行于密封剂的底表面的凹陷平面上。 位于密封剂顶表面的内部引线之间的高度是内部引线和底部表面之间的高度的三倍或更大。 由于第二芯片的数量和厚度受到控制，密封剂的顶表面与第二芯片中最相邻的芯片之间的瓦片厚度与密封剂的内部引线和底部表面之间的厚度大致相同 。 因此，密封剂中引线没有下弯曲的内部引线可平衡上下模流，并承载更多的芯片而不会移位或倾斜。

公开(公告)号：US07619305B2

公开(公告)日：2009-11-17

申请号：US11889693

申请日：2007-08-15

申请人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ron Iwata

发明人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ron Iwata

IPC分类号： H01L23/02 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/488 ,  H01L23/485

CPC分类号： H05K3/3436 ,  H01L23/13 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/83856 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K2201/0367 ,  H05K2201/0379 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked semiconductor device primarily comprises semiconductor packages with a plurality of micro contacts and solder paste to soldering the micro contacts. Each semiconductor package comprises a substrate and a chip disposed on the substrate. The micro contacts of the bottom semiconductor package are a plurality of top bumps located on the upper surface of the substrate. The micro contacts of the top semiconductor package are a plurality of bottom bumps located on the lower surface of the substrate. The bottom bumps are aligned with the top bumps and are electrically connected each other by the solder paste. Therefore, the top bumps and the bottom bumps have the same soldering shapes and dimensions for evenly soldering to avoid breakages of the micro bumps during stacking.

公开(公告)号：US20090160041A1

公开(公告)日：2009-06-25

申请号：US12071611

申请日：2008-02-25

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/498

CPC分类号： H01L23/5386 ,  H01L21/565 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate package structure is disclosed herein. The substrate package structure includes a packaging substrate provided with a plurality of chip carriers set at one surface of the packaging substrate, wherein those chip carriers are formed by intersecting a plurality of cutting streets; a plurality of through holes set at those cutting streets and set around those chip carriers; and a plurality of molding areas set on another surface of the packaging substrate and opposite to those chip carriers, wherein those molding areas are adjacent to those through holes. Hence, those through holes may be flowed by the molding compound to form a plurality of molding bumps around those chip carriers so as to improve the crack problem of the chip and/or the substrate.

摘要翻译： 本文公开了一种衬底封装结构。 衬底封装结构包括设置有设置在封装衬底的一个表面处的多个芯片载体的封装衬底，其中这些芯片载体通过与多个切割街道相交而形成; 设置在那些切割街道处的多个通孔并围绕这些芯片载体设置; 以及设置在所述包装基板的另一表面上且与所述芯片载体相对的多个模制区域，其中所述模制区域与所述通孔相邻。 因此，这些通孔可以通过模塑料流动，以在这些芯片载体周围形成多个模制凸块，从而改善芯片和/或基板的裂纹问题。

公开(公告)号：US20090127678A1

公开(公告)日：2009-05-21

申请号：US11984771

申请日：2007-11-21

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stacked assembly of semiconductor packages primarily comprises a plurality of stacked semiconductor packages. Each semiconductor package includes an encapsulant, at least a chip, and a plurality of external leads of a leadframe, where the external leads are exposed and extended from a plurality of sides of the encapsulant. Each external lead of an upper semiconductor package has a U-shaped cut end when package singulation. The U-shaped cut ends are configured for locking to the soldered portion of a corresponding external lead of a lower semiconductor package where the U-shaped cut ends and the soldered portions by soldering materials. Therefore, the stacked assembly has a larger soldering area and stronger lead reliability to enhance the soldering points to against the effects of impacts, thermal shocks, and thermal cycles.

摘要翻译： 半导体封装的堆叠组件主要包括多个堆叠的半导体封装。 每个半导体封装包括密封剂，至少芯片和引线框架的多个外部引线，其中外部引线从密封剂的多个侧面暴露和延伸。 当封装分割时，上半导体封装的每个外部引线具有U形切割端。 U形切割端被构造成用于通过焊接材料锁定到U形切割端的下半导体封装的相应外部引线的焊接部分和焊接部分。 因此，堆叠组件具有更大的焊接面积和更强的导线可靠性，以增强焊接点以抵抗冲击，热冲击和热循环的影响。