公开(公告)号：US07461199B2

公开(公告)日：2008-12-02

申请号：US11611706

申请日：2006-12-15

申请人： Kevin M. Conley ,  Yoram Cedar

发明人： Kevin M. Conley ,  Yoram Cedar

IPC分类号： G06F5/06 ,  G11C7/10 ,  G11C16/06

CPC分类号： G11C16/105 ,  G11C16/10 ,  G11C16/102 ,  G11C2216/22

摘要： The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers. Two sets of embodiments are presented, one that preserves the host data in a buffer until successful programming of that data is confirmed and one that does not require that success be achieved and that does not preserve the data thus achieving a higher rate of data programming throughput.

摘要翻译： 本发明允许在非易失性存储器系统中增加编程并行性，而不会引起额外的数据传输等待时间。 数据从控制器传送到第一存储器芯片，并且开始编程操作。 当该第一存储器芯片正在忙于执行该程序操作时，数据从控制器传送到第二存储器芯片，并且使该编程操作在该芯片中开始。 一旦完成编程操作，即使第二个芯片仍在忙于执行其程序操作，数据传输也可以再次开始到第一个存储器芯片。 以这种方式，实现编程操作的高并行性，而不会导致执行附加数据传输的延迟成本。 呈现了两组实施例，一种将缓冲器中的主机数据保留，直到该数据的成功编程被确认为止，并且不需要实现该成功，并且不保留数据从而实现更高的数据编程吞吐量 。

公开(公告)号：US07379330B2

公开(公告)日：2008-05-27

申请号：US11270198

申请日：2005-11-08

申请人： Kevin M. Conley ,  Yoram Cedar

发明人： Kevin M. Conley ,  Yoram Cedar

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C29/81 ,  G11C16/0483 ,  G11C16/16 ,  G11C29/808 ,  G11C29/82

摘要： In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme or firmware in the memory controller can implement the scheme.

摘要翻译： 在具有冗余列的存储器阵列中，一种方案允许故障单元被单独地重新映射到冗余列中的冗余单元。 一个冗余列中的冗余单元格可以替换多个非冗余列中的有缺陷单元。 重新映射作为初始测试和配置的一部分完成。 具体硬件可用于方案或固件在内存控制器中可实现的方案。

公开(公告)号：US20070136639A1

公开(公告)日：2007-06-14

申请号：US11285992

申请日：2005-11-22

申请人： Daniel Guterman ,  Yoram Cedar ,  Charles Schroter ,  Milton Barrocas ,  Carlos Gonzalez ,  Kevin Conley

发明人： Daniel Guterman ,  Yoram Cedar ,  Charles Schroter ,  Milton Barrocas ,  Carlos Gonzalez ,  Kevin Conley

IPC分类号： G11C29/00

CPC分类号： G06F13/1694 ,  G06F11/1068 ,  G11C7/00

摘要： A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.

摘要翻译： 非易失性存储器件具有控制器，并且包括控制存储器操作并模拟传统存储器件的存储器和通信特性的方法。 以这种方式，存储器设备与最初设计用于操作传统存储设备的主机兼容。 特别地，控制器考虑到诸如多位存储器，错误校正要求，覆盖的存储器支持以及可擦除块大小之类的差异，对主机执行仿真。

公开(公告)号：US06820148B1

公开(公告)日：2004-11-16

申请号：US09641023

申请日：2000-08-17

申请人： Yoram Cedar ,  Micky Holtzman ,  Yosi Pinto

发明人： Yoram Cedar ,  Micky Holtzman ,  Yosi Pinto

IPC分类号： G06F1300

CPC分类号： G06F13/1694 ,  G06F12/0653 ,  G06F12/0661 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2213/0052

摘要： Two or more very small encapsulated electronic circuit cards to which data are read and written are removably inserted into two or more sockets of a host system that is wired to the sockets. According to one aspect of the disclosure, command and response signals are normally communicated between the host and the cards by a single circuit commonly connected between the host and all of the sockets but during initialization of the system a unique relative card address is confirmed to have been written into each card inserted into the sockets by connecting the command and status circuit to each socket one at a time in sequence. This is a fast and relatively simple way of setting card addresses upon initialization of such a system. According to a second aspect of the disclosure, the host adapts to transferring data between it and different cards of the system over at least two different number of the data lines commonly connected between the host and all of one or more sockets, each card permanently storing a host readable indication of the number of parallel data lines the card is capable of using. This allows increasing the rate of data transfer when the need justifies an increased card circuit complexity. According to a third aspect of the disclosure, a serial stream of data is sent over a number of data lines from one to many by alternately connecting bits of the stream to a particular number of individual lines.

公开(公告)号：USD445111S1

公开(公告)日：2001-07-17

申请号：US29119088

申请日：2000-02-23

申请人： Kosei Okamoto ,  Takashi Torii ,  Yosi Pinto ,  Dan Auclair ,  Yoram Cedar ,  Bob Wallace

设计人： Kosei Okamoto ,  Takashi Torii ,  Yosi Pinto ,  Dan Auclair ,  Yoram Cedar ,  Bob Wallace

公开(公告)号：US20120061459A1

公开(公告)日：2012-03-15

申请号：US13209788

申请日：2011-08-15

申请人： Eliyahou Harari ,  Yoram Cedar ,  Wesley G. Brewer ,  Yosi Pinto ,  Reuven Elhamias ,  Micky Holtzman

发明人： Eliyahou Harari ,  Yoram Cedar ,  Wesley G. Brewer ,  Yosi Pinto ,  Reuven Elhamias ,  Micky Holtzman

IPC分类号： G06K19/067 ,  G06F17/00

CPC分类号： G06K19/07 ,  G06K19/0719 ,  G06K19/077 ,  G06K19/07732 ,  G06K19/07733 ,  G06K19/07743

摘要： A memory card of one published standard, such as the Multi-Media Card (MMC) or Secure Digital Card (SD), is modified to include the function of a Subscriber Identity Module (SIM) according to another published standard. The controller of the memory card communicates between electrical contacts on the outside of the card and both the memory and the SIM. In one specific form, the memory card has the physical configuration of the current Plug-in SIM card with a few external contacts added to accommodate the memory controller and data memory. In another specific form, the memory card has the physical configuration of the current SD card, including external contacts.

摘要翻译： 根据另一个发布的标准，修改了一个已发布标准的存储卡，例如多媒体卡（MMC）或安全数字卡（SD））以包括订户身份模块（SIM）的功能。 存储卡的控制器在卡的外部的电触点和存储器和SIM卡之间通信。 在一种具体形式中，存储卡具有当前插件SIM卡的物理配置，其中添加了少量外部联系以容纳存储器控制器和数据存储器。 在另一个具体形式中，存储卡具有当前SD卡的物理配置，包括外部触点。

公开(公告)号：US08027165B2

公开(公告)日：2011-09-27

申请号：US10888599

申请日：2004-07-08

申请人： Robert F. Wallace ,  Edwin J. Cuellar ,  Eliyahou Harari ,  Yoram Cedar

发明人： Robert F. Wallace ,  Edwin J. Cuellar ,  Eliyahou Harari ,  Yoram Cedar

IPC分类号： H05K1/14

CPC分类号： G06K19/07732 ,  G06K19/0723

摘要： A flash memory card structure with an external contact structure according to a published standard, such as the USB standard, also includes a second data transmission path, such as a wireless one. A removable cap fits over the card to cover the external contacts when they are not being used as a memory data path. One of two or more different caps may be selected to be placed on the card in order to control operation of the second data transmission path, such as to select the distance of wireless transmission from one of two or more pre-set distances. Power to operate the memory card through the second path, when not connected to a host, may also be provided through the external contacts by including a battery in the caps.

摘要翻译： 具有诸如USB标准的公开标准的具有外部接触结构的闪存卡结构还包括诸如无线的第二数据传输路径。 当不被用作存储器数据路径时，可拆卸的盖子可以卡在卡上以覆盖外部触点。 可以选择将两个或更多个不同的盖中的一个放置在卡上以便控制第二数据传输路径的操作，例如从两个或更多个预定距离之一选择无线传输的距离。 通过在电池盖中包含电池，也可以通过外部触点提供未连接到主机时通过第二路径操作存储卡的电源。

公开(公告)号：US20090240854A1

公开(公告)日：2009-09-24

申请号：US12477341

申请日：2009-06-03

申请人： Yoram Cedar ,  Michael Holtzman ,  Yosi Pinto

发明人： Yoram Cedar ,  Michael Holtzman ,  Yosi Pinto

IPC分类号： G06F13/00 ,  G06F12/02

CPC分类号： G06F13/1694 ,  G06F12/0653 ,  G06F12/0661 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2213/0052

摘要： Two or more very small encapsulated electronic circuit cards to which data are read and written are removably inserted into two or more sockets of a host system that is wired to the sockets. According to one aspect of the disclosure, command and response signals are normally communicated between the host and the cards by a single circuit commonly connected between the host and all of the sockets but during initialization of the system a unique relative card address is confirmed to have been written into each card inserted into the sockets by connecting the command and status circuit to each socket one at a time in sequence. This is a fast and relatively simple way of setting card addresses upon initialization of such a system. According to a second aspect of the disclosure, the host adapts to transferring data between it and different cards of the system over at least two different number of the data lines commonly connected between the host and all of one or more sockets, each card permanently storing a host readable indication of the number of parallel data lines the card is capable of using. This allows increasing the rate of data transfer when the need justifies an increased card circuit complexity. According to a third aspect of the disclosure, a serial stream of data is sent over a number of data lines from one to many by alternately connecting bits of the stream to a particular number of individual lines.

摘要翻译： 读取和写入数据的两个或更多个非常小的封装的电子电路卡可移除地插入连接到插座的主机系统的两个或更多个插槽中。 根据本公开的一个方面，命令和响应信号通常由主机与所有插座之间通用连接的单个电路在主机和卡之间进行通信，但是在系统初始化期间，唯一的相关卡地址被确认具有 通过将命令和状态电路一次一个地连接到每个插座，将其写入插入插座的每个卡中。 这是在这种系统初始化时设置卡地址的快速而相对简单的方式。 根据本公开的第二方面，主机适应于通过在主机与所有一个或多个插座之间共同连接的至少两个不同数量的数据线在其与系统的不同卡之间传送数据，每个卡永久存储 该卡能够使用的并行数据线的数量的主机可读指示。 当需要证明增加的卡电路复杂性时，这允许增加数据传输速率。 根据本公开的第三方面，通过将流的比特交替地连接到特定数量的单独线路，通过多个数据线从一个到多个数据线发送串行数据流。

公开(公告)号：US20070130405A1

公开(公告)日：2007-06-07

申请号：US11673958

申请日：2007-02-12

申请人： Yoram Cedar ,  Michael Holtzman ,  Yosi Pinto

发明人： Yoram Cedar ,  Michael Holtzman ,  Yosi Pinto

IPC分类号： H05K7/10 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/1694 ,  G06F12/0653 ,  G06F12/0661 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2213/0052

摘要： Two or more very small encapsulated electronic circuit cards to which data are read and written are removably inserted into two or more sockets of a host system that is wired to the sockets. According to one aspect of the disclosure, command and response signals are normally communicated between the host and the cards by a single circuit commonly connected between the host and all of the sockets but during initialization of the system a unique relative card address is confirmed to have been written into each card inserted into the sockets by connecting the command and status circuit to each socket one at a time in sequence. This is a fast and relatively simple way of setting card addresses upon initialization of such a system. According to a second aspect of the disclosure, the host adapts to transferring data between it and different cards of the system over at least two different number of the data lines commonly connected between the host and all of one or more sockets, each card permanently storing a host readable indication of the number of parallel data lines the card is capable of using. This allows increasing the rate of data transfer when the need justifies an increased card circuit complexity. According to a third aspect of the disclosure, a serial stream of data is sent over a number of data lines from one to many by alternately connecting bits of the stream to a particular number of individual lines.

摘要翻译： 读取和写入数据的两个或更多个非常小的封装的电子电路卡可移除地插入连接到插座的主机系统的两个或更多个插槽中。 根据本公开的一个方面，命令和响应信号通常由主机与所有插座之间通用连接的单个电路在主机和卡之间进行通信，但是在系统初始化期间，唯一的相关卡地址被确认具有 通过将命令和状态电路一次一个地连接到每个插座，将其写入插入插座的每个卡中。 这是在这种系统初始化时设置卡地址的快速而相对简单的方式。 根据本公开的第二方面，主机适应于通过在主机与所有一个或多个插座之间共同连接的至少两个不同数量的数据线在其与系统的不同卡之间传送数据，每个卡永久存储 该卡能够使用的并行数据线的数量的主机可读指示。 当需要证明增加的卡电路复杂性时，这允许增加数据传输速率。 根据本公开的第三方面，通过将流的比特交替地连接到特定数量的单独线路，通过多个数据线从一个到多个数据线发送串行数据流。

公开(公告)号：US20070103978A1

公开(公告)日：2007-05-10

申请号：US11270410

申请日：2005-11-08

申请人： Kevin Conley ,  Yoram Cedar

发明人： Kevin Conley ,  Yoram Cedar

IPC分类号： G11C16/06

CPC分类号： G11C29/81 ,  G11C16/0483 ,  G11C16/16 ,  G11C29/808 ,  G11C29/82

摘要： In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme or firmware in the memory controller can implement the scheme.

摘要翻译： 在具有冗余列的存储器阵列中，一种方案允许故障单元被单独地重新映射到冗余列中的冗余单元。 一个冗余列中的冗余单元格可以替换多个非冗余列中的有缺陷单元。 重新映射作为初始测试和配置的一部分完成。 具体硬件可用于方案或固件在内存控制器中可实现的方案。