公开(公告)号：US11004833B1

公开(公告)日：2021-05-11

申请号：US16792560

申请日：2020-02-17

Applicant: XILINX, INC.

Inventor： Anil Kumar Kandala ,  Vijay Kumar Koganti ,  Santosh Yachareni ,  Sundeep Ram Gopal Agarwal

IPC: H01L25/065 ,  H01L23/48

Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. Neighboring chips are connected to each other. Plural chips of the chips collectively include columns of broken via pillars and bridges. Each of the plural chips has a broken via pillar in each column. The broken via pillar has first and second continuous via pillar portions aligned in a direction normal to a side of a semiconductor substrate of the respective chip. The first continuous via pillar portion is not connected within the broken via pillar to the second continuous via pillar portion. Each of the plural chips has one or more of the bridges. Each bridge connects, within the respective chip, the first continuous via pillar portion in a column and the second continuous via pillar portion in another column.