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38 条记录 (耗时 0.028 秒)

    Electrostatic discharge (ESD) protection device
    11.
    发明授权
    Electrostatic discharge (ESD) protection device 有权
    静电放电（ESD）保护装置

    公开(公告)号：US08817434B2

    公开(公告)日：2014-08-26

    申请号：US13270298

    申请日：2011-10-11

    申请人： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    发明人： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC分类号： H02H9/00

    CPC分类号： H02H9/00 ,  H01L27/0266

    摘要： An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit.

    摘要翻译： 示例性ESD保护装置适用于高耐压I / O电路，并且包括堆叠晶体管和栅极接地晶体管，例如非轻掺杂漏极型栅极接地晶体管。 堆叠晶体管和栅极接地晶体管在I / O焊盘和高耐压I / O电路的接地电压之间并联电耦合。

    Buried contact method to release plasma-induced charging damage on device
    14.
    发明授权
    Buried contact method to release plasma-induced charging damage on device 失效
    埋地接触法释放等离子体对装置的充电损伤

    公开(公告)号：US5691234A

    公开(公告)日：1997-11-25

    申请号：US511065

    申请日：1995-08-03

    申请人： Kuan-Cheng Su ,  Shing-Ren Sheu

    发明人： Kuan-Cheng Su ,  Shing-Ren Sheu

    IPC分类号： H01L27/02 ,  H01L21/28

    CPC分类号： H01L27/0255

    摘要： A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

    摘要翻译： 描述了在集成电路的制造期间消除等离子体引起的充电损坏的方法。 提供具有第一导电类型的半导体衬底。 在半导体基板上形成氧化物层。 在氧化物层中形成开口。 在氧化物层和开口中形成多晶硅层。 扩散区形成在半导体衬底中，通过开口与多晶硅层连接，具有与第一导电类型相反的第二导电类型，由此形成掩埋接触。 埋入触点通过基板连接到地面参考。 进行等离子体环境中的进一步处理，这通常会对集成电路造成充电损坏，但由此埋入触点防止充电损坏。

    ELECTROSTATIC DISCHARGE (ESD) DEVICE AND SEMICONDUCTOR STRUCTURE
    15.
    发明申请
    ELECTROSTATIC DISCHARGE (ESD) DEVICE AND SEMICONDUCTOR STRUCTURE 有权
    静电放电（ESD）器件和半导体结构

    公开(公告)号：US20130113045A1

    公开(公告)日：2013-05-09

    申请号：US13290399

    申请日：2011-11-07

    申请人： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    发明人： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC分类号： H01L29/78

    CPC分类号： H01L29/78 ,  H01L27/0266 ,  H01L29/41758 ,  H01L29/4966

    摘要： An electrostatic discharge (ESD) device is described, including a gate line, a source region at a first side of the gate line, a comb-shaped drain region disposed at a second side of the gate line and having comb-teeth parts, a salicide layer on the source region and the drain region, and contact plugs on the salicide layer on the source region and the drain region. Each comb-teeth part has thereon, at a tip portion thereof, at least one of the contact plugs.

    摘要翻译： 描述了静电放电（ESD）器件，包括栅极线，栅极线第一侧的源极区域，设置在栅极线的第二侧并具有梳齿部分的梳状漏极区域， 源极区域和漏极区域上的自对准硅化物层，以及源极区域和漏极区域上的自对准硅化物层上的接触塞。 每个梳齿部分在其顶端部分上具有至少一个接触塞。

    ESD protection circuit and ESD protection device thereof
    16.
    发明申请
    ESD protection circuit and ESD protection device thereof 有权
    ESD保护电路及其ESD保护装置

    公开(公告)号：US20120170160A1

    公开(公告)日：2012-07-05

    申请号：US12981521

    申请日：2010-12-30

    申请人： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    发明人： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC分类号： H02H9/00

    CPC分类号： H02H3/20 ,  H01L27/0262 ,  H01L2924/1301 ,  H01L2924/1304 ,  H02H9/04 ,  H02H9/046

    摘要： The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.

    摘要翻译： ESD保护电路电连接在第一电力轨道和第二电力轨道之间，并且包括ESD保护装置，电连接在ESD保护装置和第一电力轨道之间的开关装置和电连接在第一电力轨道之间的低通滤波器 第一电力轨道和第一开关装置。 ESD保护器件包括BJT和电连接在BJT的基极和第一电源轨之间的第一电阻器。 当不发生ESD事件时，基极的电位大于或等于BJT发射极的电位。 当ESD事件发生时，基极的电位小于发射极的电位。

    Method for fabricating a test structure
    17.
    发明授权
    Method for fabricating a test structure 失效
    制造测试结构的方法

    公开(公告)号：US07759957B2

    公开(公告)日：2010-07-20

    申请号：US11829104

    申请日：2007-07-27

    申请人： Wen-Hsiung Ko ,  Wen-Chun Chang ,  Kuan-Cheng Su

    发明人： Wen-Hsiung Ko ,  Wen-Chun Chang ,  Kuan-Cheng Su

    IPC分类号： G01R31/02 ,  H01L21/66

    CPC分类号： G01R31/2875 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a test structure, in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by the heating plate and the electric input/output into/from the structure to be tested are controlled separately and not influenced each other.

    摘要翻译： 一种用于制造测试结构的方法，其中在晶片上形成加热板，用于加热位于加热板上方或附近的待测试结构。 加热板通过电连接到电流产生热量。 因此，加热板提供的热量和进入/待测结构的电输入/输出分开控制，彼此不相互影响。

    Method of manufacture of multi-state mask ROM and multi-state mask ROM device produced thereby
    19.
    发明授权
    Method of manufacture of multi-state mask ROM and multi-state mask ROM device produced thereby 失效
    由此制造多状态掩模ROM和多状态掩模ROM器件的方法

    公开(公告)号：US5585297A

    公开(公告)日：1996-12-17

    申请号：US450298

    申请日：1995-05-25

    申请人： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

    发明人： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

    IPC分类号： H01L27/112 ,  H01L21/8246

    CPC分类号： H01L27/112

    摘要： This is a method of manufacturing a multiple state MASK ROM semiconductor device on a P-type semiconductor substrate. The substrate includes an array of parallel buried bit lines oriented in a first direction. The process includes forming a gate oxide layer over the substrate including the buried bit lines; word lines over the gate oxide layer oriented orthogonally to the direction of the array of bit lines. Then form a first patterned implant mask over the device with a first set of openings through the mask. Ion implant dopant of a first dosage level through the openings in the mask to form implant doped regions of a first dosage level in the substrate. Form a second patterned implant mask over the device with a second set of openings through the mask. Then ion implant a dopant of a second dosage level through the openings in the mask to form implanted doped regions of a second dosage level in the substrate, the second dosage level being substantially different from the first dosage level.

    摘要翻译： 这是在P型半导体衬底上制造多状态MASK ROM半导体器件的方法。 衬底包括沿第一方向定向的平行掩埋位线阵列。 该方法包括在包括掩埋位线的衬底上形成栅氧化层; 栅极氧化物层上的字线与位线阵列的方向正交定向。 然后在装置上形成第一图案化植入物掩模，其中第一组开口穿过掩模。 通过掩模中的开口具有第一剂量水平的离子注入掺杂剂，以在衬底中形成第一剂量水平的注入掺杂区域。 在设备上形成第二图案化植入物掩模，其中第二组开口穿过掩模。 然后通过掩模中的开口离子注入第二剂量水平的掺杂剂，以在底物中形成第二剂量水平的注入的掺杂区域，第二剂量水平基本上不同于第一剂量水平。

    ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE
    20.
    发明申请
    ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE 有权
    静电放电（ESD）保护装置

    公开(公告)号：US20130088800A1

    公开(公告)日：2013-04-11

    申请号：US13270298

    申请日：2011-10-11

    申请人： Chang-Tzu WANG ,  Tien-Hao Tang ,  Kuan-Cheng Su

    发明人： Chang-Tzu WANG ,  Tien-Hao Tang ,  Kuan-Cheng Su

    IPC分类号： H02H9/00

    CPC分类号： H02H9/00 ,  H01L27/0266

    摘要： An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit.

    摘要翻译： 示例性ESD保护装置适用于高耐压I / O电路，并且包括堆叠晶体管和栅极接地晶体管，例如非轻掺杂漏极型栅极接地晶体管。 堆叠晶体管和栅极接地晶体管在I / O焊盘和高耐压I / O电路的接地电压之间并联电耦合。