公开(公告)号：US07030464B2

公开(公告)日：2006-04-18

申请号：US10791381

申请日：2004-03-03

申请人： Yuri Masuoka ,  Naohiko Kimizuka

发明人： Yuri Masuoka ,  Naohiko Kimizuka

IPC分类号： H01L29/167

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/7833 ,  Y10S257/917

摘要： A technology of restraining junction leakage in a semiconductor device is to be provided. There is provided a semiconductor device provided with a semiconductor substrate, a gate electrode 9 formed on the semiconductor substrate, and a source/drain region formed beside the gate electrode, wherein the source/drain region 4 comprises a first impurity diffusion region including a first P-type impurity and located in the proximity of a surface of the semiconductor substrate, and a second P-type impurity diffusion region located below the first impurity diffusion region and including a second P-type impurity having a smaller diffusion coefficient in the semiconductor substrate than the first P-type impurity.

摘要翻译： 要提供抑制半导体器件中的结漏电的技术。 提供了一种设置有半导体衬底的半导体器件，形成在半导体衬底上的栅极电极9和形成在栅电极旁边的源极/漏极区域，其中源/漏区域4包括第一杂质扩散区域，第一杂质扩散区域包括第一 位于半导体衬底的表面附近的P型杂质和位于第一杂质扩散区下方的第二P型杂质扩散区，并且在半导体衬底中包括具有较小扩散系数的第二P型杂质 比第一种P型杂质。

公开(公告)号：US08324090B2

公开(公告)日：2012-12-04

申请号：US12338787

申请日：2008-12-18

申请人： Yuri Masuoka ,  Peng-Fu Hsu ,  Huan-Tsung Huang ,  Kuo-Tai Huang ,  Yong-Tian Hou ,  Carlos H. Diaz

发明人： Yuri Masuoka ,  Peng-Fu Hsu ,  Huan-Tsung Huang ,  Kuo-Tai Huang ,  Yong-Tian Hou ,  Carlos H. Diaz

IPC分类号： H01L21/4763 ,  H01L25/11 ,  H01L29/78

CPC分类号： H01L29/4925 ,  H01L21/28061 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和 第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层 所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。 第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和 金属层。

公开(公告)号：US20100052063A1

公开(公告)日：2010-03-04

申请号：US12338787

申请日：2008-12-18

申请人： Yuri Masuoka ,  Peng-Fu Hsu ,  Huan-Tsung Huang ,  Kuo-Tai Huang ,  Carlos H. Diaz ,  Yong-Tian Hou

发明人： Yuri Masuoka ,  Peng-Fu Hsu ,  Huan-Tsung Huang ,  Kuo-Tai Huang ,  Carlos H. Diaz ,  Yong-Tian Hou

IPC分类号： H01L25/11 ,  H01L21/4763 ,  H01L29/78

CPC分类号： H01L29/4925 ,  H01L21/28061 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region. The first gate stack includes the high-k dielectric layer, the first capping layer, the layer containing Si, and the metal layer and the second gate stack includes the high-k dielectric layer, the second capping layer, the layer containing Si, and the metal layer.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底，提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，形成第一覆盖层和 第二覆盖层覆盖在高k电介质层上，覆盖第一区域的第一覆盖层和覆盖第二区域的第二封盖层，在第一和第二覆盖层上形成含有硅（Si）的层，形成金属层 所述层包含Si，并且在所述第一区域上形成第一栅极堆叠，并且在所述第二有源区域上形成第二栅极堆叠。 第一栅极堆叠包括高k电介质层，第一覆盖层，含有Si的层，金属层和第二栅极堆叠包括高k电介质层，第二覆盖层，含有Si的层和 金属层。

公开(公告)号：US08679926B2

公开(公告)日：2014-03-25

申请号：US13232154

申请日：2011-09-14

申请人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

发明人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。 栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

公开(公告)号：US08258587B2

公开(公告)日：2012-09-04

申请号：US12561358

申请日：2009-09-17

申请人： Yuri Masuoka ,  Shyh-Horng Yang ,  Peng-Soon Lim

发明人： Yuri Masuoka ,  Shyh-Horng Yang ,  Peng-Soon Lim

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28114 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/7833

摘要： The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a metal gate layer on the high k dielectric material layer; forming a top gate layer on the metal gate layer; patterning the top gate layer, the metal gate layer and the high k dielectric material layer to form a gate stack; performing an etching process to selectively recess the metal gate layer; and forming a gate spacer on sidewalls of the gate stack.

摘要翻译： 本公开提供了制造具有金属栅极叠层的半导体器件的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在高k电介质材料层上形成金属栅极层; 在所述金属栅极层上形成顶栅层; 图案化顶栅层，金属栅极层和高k电介质材料层以形成栅叠层; 执行蚀刻工艺以选择性地凹陷金属栅极层; 以及在所述栅极堆叠的侧壁上形成栅极间隔物。

公开(公告)号：US20120003804A1

公开(公告)日：2012-01-05

申请号：US13232154

申请日：2011-09-14

申请人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

发明人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。 栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

公开(公告)号：US08030718B2

公开(公告)日：2011-10-04

申请号：US12424170

申请日：2009-04-15

申请人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

发明人： Huan-Tsung Huang ,  Shyh-Horng Yang ,  Yuri Masuoka ,  Ken-Ichi Goto

IPC分类号： H01L29/76

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having a source region and a drain region, defining a first dimension from the source to drain; and a gate stack disposed on the semiconductor substrate and partially interposed between the source region and the drain region. The gate stack includes a high k dielectric layer disposed on the semiconductor substrate; a first metal feature disposed on the high k dielectric layer, the first metal gate feature having a first work function and defining a second dimension parallel with the first dimension; and a second metal feature having a second work function different from the first work function and defining a third dimension parallel with the first dimension, the third dimension being less than the second dimension.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括具有源极区和漏极区的半导体衬底，限定从源极到漏极的第一维度; 以及设置在所述半导体衬底上并部分插入在所述源极区域和所述漏极区域之间的栅极堆叠。 栅极堆叠包括设置在半导体衬底上的高k电介质层; 第一金属特征设置在高k电介质层上，第一金属栅极特征具有第一功函数并限定与第一维平行的第二维度; 以及具有不同于所述第一功函数的第二功函数并且限定与所述第一尺寸平行的第三尺寸的第二金属特征，所述第三尺寸小于所述第二尺寸。

公开(公告)号：US08357581B2

公开(公告)日：2013-01-22

申请号：US13217442

申请日：2011-08-25

申请人： Yuri Masuoka ,  Huan-Tsung Huang

发明人： Yuri Masuoka ,  Huan-Tsung Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

摘要： The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.

摘要翻译： 本公开提供了制造具有金属栅极叠层的半导体器件的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成第一金属层; 在所述第一金属层上形成硅层; 图案化硅层，第一金属层和高k电介质材料层以形成栅叠层; 并进行硅化处理以完全将硅层改变为硅化物电极。

公开(公告)号：US20110303991A1

公开(公告)日：2011-12-15

申请号：US13217442

申请日：2011-08-25

申请人： Yuri Masuoka ,  Huan-Tsung Huang

发明人： Yuri Masuoka ,  Huan-Tsung Huang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

摘要： The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.

摘要翻译： 本公开提供了制造具有金属栅极叠层的半导体器件的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成第一金属层; 在所述第一金属层上形成硅层; 图案化硅层，第一金属层和高k电介质材料层以形成栅叠层; 并进行硅化处理以完全将硅层改变为硅化物电极。

公开(公告)号：US08012817B2

公开(公告)日：2011-09-06

申请号：US12437696

申请日：2009-05-08

申请人： Yuri Masuoka ,  Huan-Tsung Huang

发明人： Yuri Masuoka ,  Huan-Tsung Huang

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/78 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

摘要： The present disclosure provides a method for making a semiconductor device having metal gate stacks. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a first metal layer on the high k dielectric material layer; forming a silicon layer on the first metal layer; patterning the silicon layer, the first metal layer and the high k dielectric material layer to form a gate stack; and performing a silicidation process to fully change the silicon layer into a silicide electrode.

摘要翻译： 本公开提供了制造具有金属栅极叠层的半导体器件的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成第一金属层; 在所述第一金属层上形成硅层; 图案化硅层，第一金属层和高k电介质材料层以形成栅叠层; 并进行硅化处理以完全将硅层改变为硅化物电极。