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    Fabricating Arrays Of Metallic Nanostructures
    12.
    发明申请
    Fabricating Arrays Of Metallic Nanostructures 失效
    制造金属纳米结构阵列

    公开(公告)号：US20090294755A1

    公开(公告)日：2009-12-03

    申请号：US12509689

    申请日：2009-07-27

    申请人： Philip J. Kuekes ,  M. Saif Islam ,  Shih-Yuan Wang ,  Alexandre M. Bratkovaski

    发明人： Philip J. Kuekes ,  M. Saif Islam ,  Shih-Yuan Wang ,  Alexandre M. Bratkovaski

    IPC分类号： H01L29/15 ,  B05C11/00

    CPC分类号： G02B6/107 ,  B82Y30/00 ,  Y10S977/712 ,  Y10S977/762 ,  Y10T29/41

    摘要： A patterned array of metallic nanostructures and fabrication thereof is described. A device comprises a patterned array of metallic columns vertically extending from a substrate. Each metallic column is formed by metallically coating one of an array of non-metallic nanowires catalytically grown from the substrate upon a predetermined lateral pattern of seed points placed thereon according to a nanoimprinting process. An apparatus for fabricating a patterned array of metallic nanostructures is also described.

    摘要翻译： 描述了金属纳米结构的图案阵列及其制造。 一种器件包括从衬底垂直延伸的金属柱的图案化阵列。 根据纳米压印方法，通过在其上放置的种子点的预定横向图案上，从衬底催化生长的非金属纳米线阵列之一金属地涂覆每个金属柱。 还描述了用于制造金属纳米结构的图案化阵列的装置。

    Nanowire interconnection and nano-scale device applications
    13.
    发明授权
    Nanowire interconnection and nano-scale device applications 失效
    纳米线互连和纳米级器件应用

    公开(公告)号：US07307271B2

    公开(公告)日：2007-12-11

    申请号：US10982051

    申请日：2004-11-05

    申请人： M. Saif Islam ,  Philip J. Kuekes ,  Shih-Yuan Wang ,  Duncan R. Stewart ,  Shashank Sharma

    发明人： M. Saif Islam ,  Philip J. Kuekes ,  Shih-Yuan Wang ,  Duncan R. Stewart ,  Shashank Sharma

    IPC分类号： H01L29/06 ,  H01L31/036

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y20/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01S5/0261 ,  H01S5/041 ,  H01S5/183 ,  H01S5/341 ,  H01S5/3412 ,  H01S5/3428 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764 ,  Y10S977/938

    摘要： A nano-colonnade structure-and methods of fabrication and interconnection thereof utilize a nanowire column grown nearly vertically from a (111) horizontal surface of a semiconductor layer to another horizontal surface of another layer to connect the layers. The nano-colonnade structure includes a first layer having the (111) horizontal surface; a second layer having the other horizontal surface; an insulator support between the first layer and the second layer that separates the first layer from the second layer. A portion of the second layer overhangs the insulator support, such that the horizontal surface of the overhanging portion is spaced from and faces the (111) horizontal surface of the first layer. The structure further includes a nanowire column extending nearly vertically from the (111) horizontal surface to the facing horizontal surface, such that the nanowire column connects the first layer to the second layer.

    摘要翻译： 纳米柱廊结构及其制造和互连方法利用从半导体层的（111）水平表面几乎垂直地生长到另一层的另一水平表面的纳米线柱，以连接这些层。 纳米柱廊结构包括具有（111）水平表面的第一层; 具有另一水平表面的第二层; 第一层和第二层之间的绝缘体支撑，其将第一层与第二层分离。 第二层的一部分突出于绝缘体支撑件上，使得伸出部分的水平表面与第一层的（111）水平表面间隔开并面对第一层的（111）水平表面。 该结构还包括从（111）水平表面几乎垂直延伸到相对的水平表面的纳米线列，使得纳米线列将第一层连接到第二层。

    Scalable, component-accessible, and highly interconnected three-dimensional component arrangement within a system
    16.
    发明授权
    Scalable, component-accessible, and highly interconnected three-dimensional component arrangement within a system 有权
    系统内可扩展的，可组件访问的和高度互连的三维组件布置

    公开(公告)号：US08214786B2

    公开(公告)日：2012-07-03

    申请号：US10935845

    申请日：2004-09-08

    申请人： Philip J. Kuekes ,  R. Stanley Williams ,  Raymond G. Beausoleil, Jr.

    发明人： Philip J. Kuekes ,  R. Stanley Williams ,  Raymond G. Beausoleil, Jr.

    IPC分类号： G06F17/50

    CPC分类号： G06F1/18 ,  G06F17/509 ,  H05K7/1444

    摘要： Embodiments of the present invention include dense, but accessible and well-interconnected component arrangements within multi-component systems, such as high-end multi-processor computer systems, and methods for constructing such arrangements. In a described embodiment, integrated-circuit-containing processing components, referred to as a “flat components,” are arranged into local blocks of intercommunicating flat components. The local flat-component blocks are arranged into interconnected, primitive multi-local-block repeating units, and the primitive local-block repeating units are layered together in a three-dimensional, regularly repeating structure that can be assembled to approximately fill any specified three-dimensional volume. The arrangement provides for relatively short, direct pathways from the surface of the specified volume to any particular local block and flat component within the three-dimensional arrangement.

    摘要翻译： 本发明的实施例包括在诸如高端多处理器计算机系统的多组件系统内的密集但可访问和良好互连的组件布置，以及用于构造这种布置的方法。 在所描述的实施例中，被称为“平面部件”的集成电路的处理部件被布置在相互连通的平面部件的局部块中。 本地平面组件块被布置成互连的原始多局部块重复单元，并且原始局部块重复单元以三维的规则重复的结构分层在一起，其可以被组装以大致填充任何指定的三 维数。 该装置提供从指定体积的表面到三维布置中的任何特定局部块和平坦部件的相对短的直接通路。

    Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding
    17.
    发明授权
    Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding 有权
    使用序列复制和错误控制编码的缺陷和容错解复用器

    公开(公告)号：US07872502B2

    公开(公告)日：2011-01-18

    申请号：US11484961

    申请日：2006-07-12

    申请人： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

    发明人： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

    IPC分类号： H03K19/094

    CPC分类号： H03K19/007 ,  G06F11/1076 ,  H03K19/00315

    摘要： One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.

    摘要翻译： 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。

    Nanoscale interconnection interface
    18.
    发明申请
    Nanoscale interconnection interface 有权
    纳米级互连接口

    公开(公告)号：US20100293518A1

    公开(公告)日：2010-11-18

    申请号：US12011175

    申请日：2008-01-23

    申请人： Philip J. Kuekes ,  J. Warren Robinett ,  Gadiel Seroussl ,  R. Stanley Williams

    发明人： Philip J. Kuekes ,  J. Warren Robinett ,  Gadiel Seroussl ,  R. Stanley Williams

    IPC分类号： G06F17/50

    CPC分类号： G11C13/0023 ,  B82Y10/00 ,  G06F11/1016 ,  G11C8/10 ,  G11C11/54 ,  G11C13/0002 ,  G11C2213/77 ,  G11C2213/81

    摘要： One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals input on k microscale address lines to 2k or fewer nanowires, employing supplemental, internal address lines to map 2k nanowire addresses to a larger, internal, n-bit address space, where n>k. A second demultiplexer embodiment of the present invention provides demultiplexing of signals input on n microscale address lines to 2k nanowires, with n>k, using 2k, well-distributed, n-bit external addresses to access the 2k nanowires. Additional embodiments of the present invention include a method for evaluating different mappings of nanowire addresses to internal address-spaces of different sizes, or to evaluate mappings of nanowires to external address-spaces of different sizes, metrics for evaluating address mapping and demultiplexer designs, and demultiplexer design methods.

    摘要翻译： 本发明的一个实施例提供了一种解复用器，其实现为纳米线交叉开关或具有电阻器状纳米线结的混合纳米线/微型信号线交叉开关。 一个实施例的解复用器提供在k个微米地址线上输入的信号到2k个或更少的纳米线的解复用，采用补充的内部地址线将2k个纳米线地址映射到更大的内部n位地址空间，其中n> k。 本发明的第二解复用器实施例使用2k，均匀分布的n位外部地址来访问2k纳米线，在n个微米级地址线上输入的信号到2k纳米线解复用n> k。 本发明的另外的实施例包括用于评估纳米线地址与不同大小的内部地址空间的不同映射的方法，或者评估纳米线与不同大小的外部地址空间的映射，用于评估地址映射和解复用器设计的度量，以及 解复用器设计方法。