公开(公告)号：US09734070B2

公开(公告)日：2017-08-15

申请号：US14921468

申请日：2015-10-23

申请人： QUALCOMM INCORPORATED

发明人： Alain Artieri ,  Subbarao Palacharla ,  Laurent Moll ,  Raghu Sankuratri ,  Kedar Bhole ,  Vinod Chamarty

IPC分类号： G06F12/08 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/127 ,  G06F12/0864 ,  G06F12/123

CPC分类号： G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/601 ,  G06F2212/62

摘要： A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.

公开(公告)号：US20170206028A1

公开(公告)日：2017-07-20

申请号：US15479795

申请日：2017-04-05

申请人： Samsung Electronics Co., Ltd.

发明人： Seongil O ,  Chankyung KIM ,  JongpiI SON

IPC分类号： G06F3/06 ,  G06F12/128

CPC分类号： G06F12/0846 ,  G06F11/1064 ,  G06F11/34 ,  G06F12/0246 ,  G06F12/0844 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/128 ,  G06F2201/885 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G11C5/04 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/40607 ,  G11C11/4093 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/32 ,  G11C29/26 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/5002 ,  G11C2207/2245

摘要： A method includes outputting, at a processor, a command and an address to the memory module, receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the memory module, from the memory module, determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting, and outputting, at the processor, the determined cache hit/miss to the memory module.

公开(公告)号：US09697126B2

公开(公告)日：2017-07-04

申请号：US14860993

申请日：2015-09-22

申请人： QUALCOMM Incorporated

发明人： Derek Robert Hower ,  Harold Wade Cain, III

IPC分类号： G06F12/08 ,  G06F11/34 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895

CPC分类号： G06F12/084 ,  G06F11/3037 ,  G06F11/3433 ,  G06F11/3466 ,  G06F11/3471 ,  G06F11/348 ,  G06F12/0846 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2112 ,  G06F2212/282 ,  G06F2212/314 ,  Y02D10/13

摘要： Generating approximate usage measurements for shared cache memory systems is disclosed. In one aspect, a cache memory system is provided. The cache memory system comprises a shared cache memory system. A subset of the shared cache memory system comprises a Quality of Service identifier (QoSID) tracking tag configured to store a QoSID tracking indicator for a QoS class. The shared cache memory system further comprises a cache controller configured to receive a memory access request comprising a QoSID, and is configured to access a cache line corresponding to the memory access request. The cache controller is also configured to determine whether the QoSID of the memory access request corresponds to a cache line assigned to the QoSID. If so, the cache controller is additionally configured to update the QoSID tracking tag.

公开(公告)号：US09639407B1

公开(公告)日：2017-05-02

申请号：US14741028

申请日：2015-06-16

申请人： Parallel Machines Ltd.

发明人： Avner Braverman ,  Michael Adda ,  Lior Amar ,  Lior Khermosh ,  Eli Finer ,  Gal Zuckerman

IPC分类号： G06F9/46 ,  G06F9/54 ,  G06F9/48 ,  G06F9/44 ,  G06F11/36

CPC分类号： G06F9/542 ,  G06F8/10 ,  G06F8/451 ,  G06F9/461 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5016 ,  G06F9/5066 ,  G06F9/544 ,  G06F11/3624 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/1081 ,  G06F13/1663 ,  G06F2212/2532

摘要： Various systems and methods to perform efficiently a first processing task in conjunction with a plurality of data sets. A first code sequence comprises a plurality of general commands, and a specific command including a description of a first data processing task to be performed in conjunction with the data sets. The general commands are received and processed in a standard manner. The specific command is identified automatically by its nature, and the description within the specific command is then converted into a first sequence of executable instructions executable by a plurality of compute elements holding the plurality of data sets. The ultimate result is an efficient implementation of the first processing task. In some embodiments, the implementation of the first processing task is assisted by a pre-defined procedure that allocates the data sets to the compute elements and shares instances of executable instructions with the compute elements.

公开(公告)号：US20170068619A1

公开(公告)日：2017-03-09

申请号：US15264045

申请日：2016-09-13

申请人： Intel Corporation

发明人： Altug Koker ,  Thomas A. Piazza ,  Murali Sundaresan

IPC分类号： G06F12/0804 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/0808

CPC分类号： G06F12/0804 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0831 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0875 ,  G06F12/128 ,  G06F2212/621

摘要： In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and addresses. Thus, such a technique may be more amenable to conventional software developers and their conventional techniques.

摘要翻译： 根据一些实施例，可以启用由系统存储器公开或支持并使用常规标签和地址的分散/收集存储器方法。 因此，这种技术可能更适合于常规软件开发者及其常规技术。

公开(公告)号：US20170060747A1

公开(公告)日：2017-03-02

申请号：US15350056

申请日：2016-11-13

申请人： HOLA NETWORKS LTD.

发明人： Derry Shribman ,  Ofer Vilenski

IPC分类号： G06F12/0846 ,  G06F12/0875 ,  G06F12/0871

CPC分类号： G06F12/0846 ,  G06F12/023 ,  G06F12/0842 ,  G06F12/0851 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/12 ,  G06F12/128 ,  G06F17/30132 ,  G06F2212/1044 ,  G06F2212/403 ,  G06F2212/452 ,  G06F2212/604 ,  G06F2212/6042 ,  G06F2212/621

摘要： A method for increasing storage space in a system containing a block data storage device, a memory, and a processor is provided. Generally, the processor is configured by the memory to tag metadata of a data block of the block storage device indicating the block as free, used, or semifree. The free tag indicates the data block is available to the system for storing data when needed, the used tag indicates the data block contains application data, and the semifree tag indicates the data block contains cache data and is available to the system for storing application data type if no blocks marked with the free tag are available to the system.

摘要翻译： 提供了一种用于增加包含块数据存储设备，存储器和处理器的系统中的存储空间的方法。 通常，处理器由存储器配置以标记块存储装置的数据块的元数据，指示块为空闲，使用或半分。 免费标签表示数据块可用于系统，用于在需要时存储数据，所使用的标签指示数据块包含应用数据，半标签表示数据块包含高速缓存数据，并且可用于存储应用数据的系统 键入，如果没有标有免费标签的块可用于系统。

公开(公告)号：US09582424B2

公开(公告)日：2017-02-28

申请号：US15186599

申请日：2016-06-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Michael K. Gschwind ,  Jose E. Moreira

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0846 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/126 ,  G06F2212/251 ,  G06F2212/602 ,  Y02D10/13

摘要： Embodiments relate to counter-based wide fetch management. An aspect includes assigning a counter to a first memory region in a main memory that is allocated to a first application that is executed by a processor of a computer. Another aspect includes maintaining, by the counter, a count of a number of times adjacent cache lines in the cache memory that correspond to the first memory region are touched by the processor. Another aspect includes determining an update to a data fetch width indicator corresponding to the first memory region based on the counter. Another aspect includes sending a hardware notification from a counter management module to supervisory software of the computer of the update to the data fetch width indicator. Yet another aspect includes updating, by the supervisory software, the data fetch width indicator of the first memory region in the main memory based on the hardware notification.

摘要翻译： 实施例涉及基于反向的宽提取管理。 一个方面包括将计数器分配给分配给由计算机的处理器执行的第一应用的主存储器中的第一存储器区域。 另一方面包括通过计数器维持与处理器接触的对应于第一存储器区域的高速缓冲存储器中的高速缓存行相邻的次数的计数。 另一方面包括基于计数器确定对应于第一存储器区域的数据获取宽度指示符的更新。 另一方面包括将来自计数器管理模块的硬件通知发送到数据获取宽度指示符的更新计算机的监控软件。 另一方面包括基于硬件通知，由监控软件更新主存储器中的第一存储器区域的数据获取宽度指示符。

公开(公告)号：US20170031606A1

公开(公告)日：2017-02-02

申请号：US14811357

申请日：2015-07-28

申请人： Futurewei Technologies, Inc.

发明人： Hao Luan ,  Alan Gatherer ,  Sriram Vishwanath ,  Casen Hunger ,  Hardik Jain

IPC分类号： G06F3/06

CPC分类号： G06F3/0611 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/108 ,  G06F11/34 ,  G06F12/0284 ,  G06F12/0607 ,  G06F12/0846 ,  G06F12/121 ,  G06F13/16 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/262 ,  G06F2212/401 ,  G06F2212/403

摘要： Systems and techniques for dynamic coding of memory regions are described. A described technique includes monitoring accesses to a group of memory regions, each region including two or more portions of a group of data banks; detecting a high-access memory region based on whether accesses to a region of the group of memory regions exceeds a threshold; generating coding values of a coding region corresponding to the high-access memory region, the high-access memory region including data values distributed across the group of banks; and storing the coding values of the coding region in a coding bank.

摘要翻译： 描述用于存储区域的动态编码的系统和技术。 所描述的技术包括监视对一组存储器区域的访问，每个区域包括一组数据库的两个或更多个部分; 基于对该组存储器区域的区域的访问是否超过阈值来检测高访问存储区域; 生成与所述高访问存储区域相对应的编码区域的编码值，所述高访问存储区域包括分布在所述存储体组中的数据值; 并将编码区域的编码值存储在编码组中。

公开(公告)号：US09558121B2

公开(公告)日：2017-01-31

申请号：US13729840

申请日：2012-12-28

申请人： INTEL CORPORATION

发明人： Li-Gao Zei ,  Fernando Latorre ,  Steffen Kosinski ,  Jaroslaw Topp ,  Varun Mohandru ,  Lutz Naethke

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0846 ,  G06F12/0864 ,  G06F12/1063

摘要： A virtually tagged cache may be configured to index virtual address entries in the cache into lockable sets based on a page offset value. When a memory operation misses on the virtually tagged cache, only the one set of virtual address entries with the same page offset may be locked. Thereafter, this general lock may be released and only an address stored in the physical tag array matching the physical address and a virtual address in the virtual tag array corresponding to the matching address stored in the physical tag array may be locked to reduce the amount and duration of locked addresses. The machine may be stalled only if a particular memory address request hits and/or tries to access one or more entries in a locked set. Devices, systems, methods, and computer readable media are provided.

摘要翻译： 虚拟标记的高速缓存可以被配置为基于页面偏移值将高速缓存中的虚拟地址条目索引到可锁定集合。 当内存操作错过虚拟标记的缓存时，只有一组具有相同页偏移量的虚拟地址条目可能被锁定。 此后，可以解除该通用锁定，并且仅锁定与物理地址匹配的物理标签阵列中存储的地址和与物理标签阵列中存储的匹配地址相对应的虚拟标签阵列中的虚拟地址，以减少数量和 锁定地址的持续时间。 只有当特定的存储器地址请求命中和/或尝试访问锁定集中的一个或多个条目时，才可能停止该机器。 提供了设备，系统，方法和计算机可读介质。

公开(公告)号：US09558120B2

公开(公告)日：2017-01-31

申请号：US14227940

申请日：2014-03-27

申请人： Intel Corporation

发明人： Dyer Rolan ,  Nevin Hyuseinova ,  Blas A. Cuesta ,  Qiong Cai

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0833 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0871 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/122 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/502 ,  G06F2212/604 ,  G06F2212/62

摘要： Techniques and mechanism to provide a cache of cache tags in determining an access to cached data. In an embodiment, a tag storage stores a first set including tags associated with respective data locations of a cache memory. A cache of cache tags store a subset of tags stored by the tag storage. In response to any determination that a tag of the first set is to be stored to the cache of cache tags, all tags of the first set are stored to the first portion. Any storage of tags of the first set to the cache of cache tags includes storage of the tags of the first set to only a first portion of the cache of cache tags. In another embodiment, a replacement table is maintained for use in determining, based on an indicated level of activity for a set of the cache of cache tags, whether the set is to be selected for eviction and replacement of cached tags.

摘要翻译： 在确定对缓存数据的访问时提供高速缓存标签缓存的技术和机制。 在一个实施例中，标签存储存储包括与高速缓冲存储器的相应数据位置相关联的标签的第一集合。 缓存标签的缓存存储标签存储器存储的标签的子集。 响应于将第一组的标签存储到高速缓存标签的高速缓存中的任何确定，第一组的所有标签都被存储到第一部分。 将第一组的标签的任何存储器存储到缓存标签的高速缓存包括将第一集合的标签仅存储在高速缓存标签的高速缓存的仅第一部分。 在另一个实施例中，维护替换表用于基于指定的高速缓存标签的高速缓存的一组指定的活动级别来确定该集合是否被选择用于缓存和替换高速缓存的标签。