-
公开(公告)号：US20180225202A1
公开(公告)日：2018-08-09
申请号：US15943883
申请日：2018-04-03
Applicant: Quantum Corporation
Inventor： Don Doerner
IPC: G06F12/0804 , G06F12/0891 , G06F12/121
CPC classification number: G06F12/0804 , G06F12/0891 , G06F12/121 , G06F2212/1044 , G06F2212/604
Abstract: Embodiments provide adaptive storage management for optimizing multi-tier data storage. A storage manager may interact with storage decision advisors. The manager may adaptively make storage management decisions (e.g., flush, evict, recall, delete) after considering recommendations from and the credibility of the storage decision advisors. The manager may update the credibility of storage decision advisors based on how their recommendations affected optimization. The manager may adaptively choose when to rebalance or reconfigure the credibility of the storage decision advisors. Storage decision advisors may themselves be adaptive. Storage decision advisors may examine credibility feedback from the storage manager to determine which recommendations were useful and which were not. Storage decision advisors may then change when they will make a recommendation, when they will abstain from making a recommendation, the type of recommendation provided, or other behavior. Optimization may concern performance, cost, power usage, or other factors.
-
12.发明申请
公开(公告)号：US20180225122A1
公开(公告)日：2018-08-09
申请号：US15879492
申请日：2018-01-25
Applicant: FUJITSU LIMITED
Inventor： Tatsuo Kumano
IPC: G06F9/38 , G06F12/0866 , G06F12/0862 , G06F3/06
CPC classification number: G06F9/3832 , G06F3/061 , G06F3/0653 , G06F3/0659 , G06F3/0685 , G06F3/0688 , G06F12/0862 , G06F12/0866 , G06F2212/312 , G06F2212/604
Abstract: A method performed by a computer for analyzing access to a storage device, the method includes: executing a calculating process that includes calculating, for each of a plurality of ranges obtained by dividing a storage area of the storage device, an access number or a variation of the access number in each of a plurality of periods, wherein the access number indicates the number of times of access to each of the plurality of ranges; and executing a determining process that includes determining a correlation between any two of the plurality of ranges in accordance with the access number or the variation of the access number for each period in each of the plurality of ranges.
-
公开(公告)号：US10042769B2
公开(公告)日：2018-08-07
申请号：US15075706
申请日：2016-03-21
Applicant: NANNING FUGUI PRECISION INDUSTRIAL CO., LTD.
Inventor： Yi-Sheng Huang
CPC classification number: G06F12/0871 , G06F11/2289 , G06F11/3051 , G06F13/4018 , G06F13/4022 , G06F2212/1024 , G06F2212/222 , G06F2212/604
Abstract: A method for managing cache space between one electronic device and multiple storage devices includes identifying and quantifying storage devices connected to an electronic device, and acquiring efficiency information of each identified storage device on preset occasions. Cache space of each storage device is computed on being connected to or being disconnected from the electronic device, taking account of information acquired as to efficiency and quantity of each of the storage devices. A core switch of the electronic device is controlled to allocate a computed cache space to a storage device.
-
公开(公告)号：US20180173433A1
公开(公告)日：2018-06-21
申请号：US15898659
申请日：2018-02-18
Applicant: MoSys, Inc.
Inventor： Michael J. Miller , Jay B. Patel , Michael J. Morrison
IPC: G06F3/06 , G06F12/0895 , G06F9/38 , G06F12/00 , G06F12/0875 , H04L29/12 , H04L29/08
CPC classification number: G06F3/0611 , G06F3/0659 , G06F3/067 , G06F9/3877 , G06F12/00 , G06F12/0875 , G06F12/0895 , G06F2212/1024 , G06F2212/452 , G06F2212/604 , H04L29/12 , H04L67/1017 , H04L67/2842
Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.
-
15.发明申请
公开(公告)号：US20180165216A1
公开(公告)日：2018-06-14
申请号：US15893150
申请日：2018-02-09
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Umesh Maheshwari
IPC: G06F12/0891 , G06F3/06 , G06F12/02 , G06F12/06 , G06F12/0802 , G06F12/0866 , G06F12/0873 , G06F12/12 , G11C7/10 , G11C14/00
CPC classification number: G06F12/0891 , G06F3/0619 , G06F3/065 , G06F3/0688 , G06F12/0246 , G06F12/0253 , G06F12/0638 , G06F12/0802 , G06F12/0866 , G06F12/0873 , G06F12/12 , G06F2212/1044 , G06F2212/205 , G06F2212/222 , G06F2212/224 , G06F2212/604 , G06F2212/70 , G06F2212/702 , G06F2212/7201 , G06F2212/7205 , G11C7/1072 , G11C14/0018
Abstract: A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The device includes a controller configured to manage the cache by consolidating information concerning obsolete data stored in the cache with information concerning data no longer desired to be stored in the cache, and erase segments of the cache containing one or more of the blocks of obsolete data and the blocks of data that are no longer desired to be stored in the cache to produce reclaimed segments of the cache.
-
公开(公告)号：US20180136849A1
公开(公告)日：2018-05-17
申请号：US15869287
申请日：2018-01-12
Applicant: TOSHIBA MEMORY CORPORATION
Inventor： Yusuke Shirota , Tatsunori Kanai , Masaya Tarui
IPC: G06F3/06 , G06F12/0808 , G06F12/0868
CPC classification number: G06F3/0607 , G06F3/061 , G06F3/0614 , G06F3/065 , G06F3/0688 , G06F9/50 , G06F12/08 , G06F12/0808 , G06F12/0831 , G06F12/0868 , G06F2212/1016 , G06F2212/1032 , G06F2212/222 , G06F2212/312 , G06F2212/604 , G06F2212/621
Abstract: According to one embodiment, a memory controller includes a nonvolatile cache memory and a controller. The nonvolatile cache memory is configured to store a piece of data stored in a nonvolatile main memory connected to the memory controller. The controller is configured to control writing of data to the nonvolatile cache memory. The memory controller is connected to a processor via an interconnect that ensures a protocol indicating a procedure for preventing data inconsistency in a plurality of cache memories. The controller causes, after detecting that the processor has updated data corresponding to any area of the nonvolatile main memory using the protocol, the updated data to be transmitted to the memory controller and writes the updated data to the nonvolatile cache memory.
-
公开(公告)号：US09971698B2
公开(公告)日：2018-05-15
申请号：US15017687
申请日：2016-02-08
Applicant: Strato Scale Ltd.
Inventor： Mike Rapoport , Abel Gordon , Ariel Maislos
IPC: G06F12/08 , G06F12/0891 , G06F3/06
CPC classification number: G06F12/0891 , G06F3/0604 , G06F3/0605 , G06F3/061 , G06F3/0631 , G06F3/0649 , G06F3/0673 , G06F3/0685 , G06F12/08 , G06F12/123 , G06F12/128 , G06F2212/604
Abstract: A method includes, in a computing system in which one or more workloads access memory pages in a memory, defining multiple memory-page lists, and specifying for each memory-page list a respective different scanning period. Access frequencies, with which the memory pages are accessed, are estimated continually by periodically checking the memory pages on each memory-page list in accordance with the scanning period specified for that memory-page list, and re-assigning the memory pages to the memory-page lists based on the estimated access frequencies. One or more of the memory pages are evicted from the memory based on a history of assignments of the memory pages to the memory-page lists.
-
公开(公告)号：US09965389B2
公开(公告)日：2018-05-08
申请号：US14841788
申请日：2015-09-01
Applicant: Quantum Corporation
Inventor： Don Doerner
IPC: G06F12/08 , G06F12/0804 , G06F12/0891 , G06F12/121
CPC classification number: G06F12/0804 , G06F12/0891 , G06F12/121 , G06F2212/1044 , G06F2212/604
Abstract: Embodiments provide adaptive storage management for optimizing multi-tier data storage. A storage manager may interact with storage decision advisors. The manager may adaptively make storage management decisions (e.g., flush, evict, recall, delete) after considering recommendations from and the credibility of the storage decision advisors. The manager may update the credibility of storage decision advisors based on how their recommendations affected optimization. The manager may adaptively choose when to rebalance or reconfigure the credibility of the storage decision advisors. Storage decision advisors may themselves be adaptive. Storage decision advisors may examine credibility feedback from the storage manager to determine which recommendations were useful and which were not. Storage decision advisors may then change when they will make a recommendation, when they will abstain from making a recommendation, the type of recommendation provided, or other behavior. Optimization may concern performance, cost, power usage, or other factors.
-
公开(公告)号：US20180121362A1
公开(公告)日：2018-05-03
申请号：US15847316
申请日：2017-12-19
Applicant: Violin Systems LLC
Inventor： Amit Garg , Vikas Ratna
IPC: G06F12/0868 , G06F12/128 , G06F3/06 , G06F17/30 , G06F12/0831
CPC classification number: G06F3/067 , G06F3/0608 , G06F3/0641 , G06F17/30132 , G06F2212/604 , G06F2212/62 , G06F2212/70
Abstract: Efficient processing of user data read requests in a deduplicated data storage system places the metadata for most frequently requested data in data structures and locations in the system hierarchy where the metadata will be most rapidly available. The total amount of such metadata makes storing all of the metadata in high speed memory expensive, and the system and method described uses both the temporal and the spatial characteristics of the user system activity in any epoch to adjust the contents of metadata cache so as to respond to the dynamics of a multi user or multi-application environment where the storage system is not made aware of the time changing mix of operations except by observation of the individual requests. A history record is used to promote metadata from the slow memory to the fast memory, and a process selection may be adjusted based on the address-space activity.
-
公开(公告)号：US20180107572A1
公开(公告)日：2018-04-19
申请号：US15841083
申请日：2017-12-13
Applicant: Dell Products L.P.
Inventor： Lucky Pratap Khemani , Kala Sampathkumar
IPC: G06F11/20 , G06F12/0893 , G06F17/30
CPC classification number: G06F11/2094 , G06F11/2092 , G06F11/2097 , G06F12/0893 , G06F16/22 , G06F2201/85 , G06F2212/604
Abstract: A storage controller failover system includes servers, storage controllers coupled to storage subsystems, and a switching system coupling the servers to the storage controllers. A storage controller configurations and storage controller caches for each of the storage controllers are stored in one or more database. A failure is detected of a first storage controller that has provided first storage communications along a first path between a first server and a first storage subsystem and, in response, a second storage controller that is configured to take over the first storage communications from the first storage controller is determined based on its second storage controller configuration. A first storage controller cache for the first storage controller is provided to the second storage controller, and the second storage controller is caused to provide the first storage communications along a second path between the first server and the first storage subsystem.
